1. Nayan Naware
  2. General
  3. Sunday, 20 October 2019
How can we write an assertion for the following condition -

A signal X can either be low for one clock cycle or it can be low for 4 clock cycle.
Responses (1)
Accepted Answer Pending Moderation

property x_assert;
@(posedge clk) $fell(x) |-> ##[1:4] $rose(x);
endproperty

assert property(x_assert);
References
  1. https://www.edaplayground.com/x/3RQE
  1. more than a month ago
  2. General
  3. # 1
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