1. Chen Yong
  2. UVM
  3. Tuesday, 18 June 2019
Hi,
Can anybody help me to understand how to end simulation with UVM? for code example UVM-301 (I also attached the code in the post), the simulation ended just after reset is deasserted. At that time there is no driving signals working. This confused me.


task reset_phase (uvm_phase phase);
super.reset_phase (phase);
phase.raise_objection (phase);
`uvm_info (get_type_name (), $sformatf ("Applying initial reset"), UVM_MEDIUM)
this.vif.rstn = 0;
repeat (20) @ (posedge vif.clk);
this.vif.rstn = 1;
`uvm_info (get_type_name (), $sformatf ("DUT is now out of reset"), UVM_MEDIUM)
phase.drop_objection (phase);
endtask

task main_phase (uvm_phase phase);
super.main_phase (phase);
forever begin
`uvm_info (get_type_name (), $sformatf ("Waiting for data from sequencer"), UVM_MEDIUM)
seq_item_port.get_next_item (data_obj);
drive_item (data_obj);
seq_item_port.item_done ();
end
endtask

virtual task drive_item (my_data data_obj);
@(posedge vif.clk);
this.vif.en = 1;
this.vif.wr = 1;
this.vif.addr = data_obj.addr;
this.vif.wdata = data_obj.data;
`uvm_info ("DRV", $sformatf ("Driving data item across DUT interface"), UVM_HIGH)
data_obj.print (uvm_default_tree_printer);
endtask

task shutdown_phase (uvm_phase phase);
super.shutdown_phase (phase);
`uvm_info (get_type_name(), "Finished DUT simulation", UVM_LOW)
endtask




regards
Yong
Attachments (1)
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Finally I find the reason why the simulation ends. In the sequence module, there is code as:


repeat (n_times) begin
// repeat (3) begin
start_item (data_obj);
assert (data_obj.randomize ());
finish_item (data_obj);
end


the variable "n_times" wasn't given any valid value so this sequence's function (start_item, etc) doesn't run. That is the reason why the simulation ends.
  1. more than a month ago
  2. UVM
  3. # Permalink
Responses (5)
Accepted Answer Pending Moderation
Hello Yong,

Your debug analysis is correct, the n_times variable was not assigned anything from the test nor was it randomized to any value and hence ended up with 0. It's a testbench bug. Good catch !
  1. more than a month ago
  2. UVM
  3. # 1
Accepted Answer Pending Moderation
Hi Admin,

thanks for your confirm. Could you please let me know how to assign a value to n_times variable from the test? thanks.
  1. more than a month ago
  2. UVM
  3. # 2
Accepted Answer Pending Moderation
Yong,

For the starter testbench illustrated in uvm-301, n_times can be passed to the sequence using a uvm_config_db set and get call.

// This is the build phase in base_test within test_pkg.sv
virtual function void build_phase (uvm_phase phase);
int n_times; // Declare n_times
super.build_phase (phase);

n_times = 10; // Assign some value or randomize this variable
m_top_env = my_env::type_id::create ("m_top_env", this);

// Get DUT interface from top module
if (! uvm_config_db #(virtual dut_if) :: get (this, "", "dut_if", vif)) begin
`uvm_error (get_type_name (), "DUT Interface not found !")
end

// Pass DUT interface to all components
uvm_config_db #(virtual dut_if) :: set(this, "m_top_env.*", "vif", vif);

// Set n_times in uvm_config_db so that this config can be retrieved in sequence
uvm_config_db #(int) :: set(null, "uvm_test_top", "n_times", n_times);
endfunction : build_phase


Then within sequence in my_pkg.sv, you can retrieve the config from uvm_config_db like:

// This is the body() task of base_sequence within my_pkg.sv
virtual task body ();
`uvm_info ("BASE_SEQ", $sformatf ("Starting body of %s", this.get_name()), UVM_MEDIUM)
data_obj = my_data::type_id::create ("data_obj");

// Get config from uvm_config_db
if (!uvm_config_db#(int):: get(null, "uvm_test_top", "n_times", n_times))
`uvm_fatal(get_type_name(), $sformatf("Did not get n_times = %0d", n_times))

repeat (n_times) begin
start_item (data_obj);
assert (data_obj.randomize ());
finish_item (data_obj);
end
`uvm_info (get_type_name (), $sformatf ("Sequence %s is over", this.get_name()), UVM_MEDIUM)
endtask


The recommended way to start a sequence is with its start() method which is better than setting the default sequence to be executed during the main_phase. I'll update the code to reflect the new style.
  1. more than a month ago
  2. UVM
  3. # 3
Accepted Answer Pending Moderation
Hi Admin,

thanks for your guidance. :D
  1. more than a month ago
  2. UVM
  3. # 4
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