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  1. Durga rao seelamsetti
  2. UVM
  3. Saturday, 20 April 2019
In uvm we use raise objection and drop objection ? What is the background process except triggering process ? 2.in case we raise phase raise and forget drop objection then what the process ?
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The idea behind an objection raise and drop is to synchronize all components before moving onto the next phase. If there are child components that has raised an objection for say, main_phase, simulation will wait until all objections have been dropped before moving to the next phase. When an objection is raised, UVM testbench structure keeps a count of how many objections it received and decrements the count as other components drop previously raised objections. If you raise an objection and do not drop it, the current phase will never end and simulation would most likely hang.
  1. 3 weeks ago
  2. UVM
  3. # Permalink
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