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  1. Venkateshwara Rao
  2. UVM
  3. Tuesday, 18 December 2018
Suppose i have a long running test say it ran for 24 hours and it encountered a UVM error. There might some more errors after this error.
I fixed the first error. Now commonly i have to run the test for 24 hours to look at further errors.
Is there a way in UVM/system verilog/VCS/questa where when i fix the first error and i dont want to waste 24 hours and run the test from the error point?
we can increase UVM_MAX_QUIT_COUNT to get the subsequent errors. but i want to rerun the test from failing point to save time.
Accepted Answer
Accepted Answer Pending Moderation
You can try the following to reduce time:

  1. Check with tool vendor to see how you can compile design/TB separately and enable incremental compilation - saves recompilation time
  2. Disable waveform dump until say 1000 ns before the place where error occurs, and select required hierarchies only for remaining simulation time
  3. If the errors are due to bad constraints, there are options in Verdi for you to try certain values on the fly to see the effect and perform interactive debug
  4. Signal states will have to be saved for the simulation to resume from the point of error, and hence you might have to check with the tool vendor to see if they have any such option.
  5. Last but the least, launch it on an LSF machine if its not being done already.

Ideally, its best to keep tests short and keep it such way that it takes max 2-3 hrs to finish. This helps to avoid large log files and waveform dumps that may crash the system. Moreover, it will save the job from consuming too much memory.
  1. more than a month ago
  2. UVM
  3. # Permalink
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