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  1. Admin
  2. Compilation & Runtime Errors
  3. Thursday, 14 June 2018
Simulation hangs with the following message :


UVM_FATAL/uvm-1.2/src/base/uvm_phase.svh(1489) @ 9200000000000: reporter [PH_TIMEOUT] Default timeout of 9200000000000 hit, indicating a probable testbench issue

--- UVM Report Summary ---


Driver was written in main_phase while the test is executed in run_phase. Somehow this caused some problem with the sequencer driver handshake not to complete and the simulation to hang.
References
  1. https://www.edaplayground.com/x/47kA
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