1. Nayan Naware
  2. UVM
  3. Friday, 31 March 2017
Backdoor and front door register access ??
Accepted Answer
Accepted Answer Pending Moderation
Thanks for asking these questions, I'll put a post on this soon.

A simple explanation is that frontdoor utilizes the register peripheral bus to drive protocol transactions to the design. This is the real use case scenario where a processor core can access the register space within the design via the peripheral bus. An example would be when the design has an APB interface for its registers, and the UVM environment sends APB transactions to the design with an address and data to read/write a particular register.

The backdoor is a technique to directly put/get the value onto the register variable in the design RTL signal, for which you have to build up the hierarchical path to the registers. Backdoor does not consume any simulation time, and is faster. But it is quite insufficient to be the only mode of verification. This is usually done during the early testbench development phase or when agents that can drive transactions to the DUT are not available.
  1. https://www.chipverify.com/uvm/uvm-register-model-example
  2. https://www.chipverify.com/uvm/uvm-register-backdoor-access
  1. more than a month ago
  2. UVM
  3. # Permalink
Responses (3)
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Can you provide me a example of frontdoor and backdoor access ?
  1. more than a month ago
  2. UVM
  3. # 1
Accepted Answer Pending Moderation
Hope this helps, these are complete examples of how frontdoor and backdoor accesses are made.

1. UVM Frontdoor Access
2. UVM Backdoor Access
  1. more than a month ago
  2. UVM
  3. # 2
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