Power of SystemVerilog Constraints

SystemVerilog constraints are pretty amazing ! Lets see one use case where constraints are used to generate two queues of random sizes with unique values. Let us assume total number of elements in each queue should be less than or equal to 10.

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Uniquely constrain variables

One of the most commonly asked questions in System Verilog for interviews is how to uniquely constrain any given array, or any two variables. There are a couple of workarounds for this, but we didn't have a clean shortcut to achieve this very useful functionality until the 2012 IEEE revision.

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