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What is SystemVerilog ?

It's a Hardware Verification Language. As you might already know, hardware (computer chips) is designed using a Hardware Description Language (VHDL, Verilog) which is then synthesized into gates like NOR, NAND and sequential elements like Flip-Flops. So before you do synthesis, which is a tedious process, you would want to make sure that the functionality aspect of your HDL-constructed design looks good.

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about the UVM queue class ?

Yes. UVM has a class-based dynamic queue that can be allocated on demand, passed and stored by reference. Eventhough uvm_queue is a parameterized class extended from uvm_object, it is not registered with the factory and hence invocation of new() function is the correct way to create a queue object.

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kumar swamy
Sir Can one one explain in detail about the virtual sequencer and sequence How is it useful for test case writer... Read More
Tuesday, 25 September 2018 09:11
Admin
Hope this helps : Virtual Sequence and Virtual Sequencer... Read More
Tuesday, 25 September 2018 09:39
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When an X on clock almost went unnoticed

One of the first few items in the checklist for a failing testcase is the clock to the module. Usually an external crystal oscillator would be fed into a PLL block within the SoC to obtain and supply derivative clocks to all other parts of the system. So if a peripheral module does not respond when its control registers are being read it would be helpful to check if the clocks to the module are running and are of the correct frequency along with top level connections.

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Suguresh Kumar Arali
Hey Admn, there is slight typo mistake in code "assign gatedClk = gateEn && clk;" please make necessary changes. and one more do... Read More
Monday, 07 August 2017 00:39
Admin
Thanks for catching that, HTML format interpreted the ampersand symbol in a different way. I just happened to see X on the clock i... Read More
Monday, 07 August 2017 06:58
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how to pass a command line argument to UVM testbench ?

At times we might need to accept values from the command line to make our testbench and testcases more flexible. UVM provides this support via the uvm_cmdline_processor singleton class. Generation of the data structures which hold the command line arguments happen during construction of the class object. A global variable called uvm_cmdline_proc is created at initialization time which can be used to access command line options. Let's see more on how this feature can be used.

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son nguyen
Hi, thanks for sharing! Is there any difference bw this and $test$plusargs ?
Saturday, 18 August 2018 04:13
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$deposit - Put a value onto any net/register

A few months ago, I was involved in writing a couple of tests that had to be run using RTL netlists with scan chains in them. Since this involved a lot of gate level signals, it was already cumbersome to debug. The idea was to enter the scan mode and shift out values in the chain and then be able to observe the value of a particular flop, after so many cycles at the output pad. So, there was a need to check if we got the right value at the pin after scan entry.

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what is the m_sequencer ?

There are primarily two ways to start a sequence : use a `uvm_do macro, or use the start() method. If you have read How to execute sequences via `uvm_do macros ?, you might already know that `uvm_do macros eventually call the start() method, and the macros act as a wrapper to execute both data items and sequences on the default sequencer "m_sequencer".

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Shrikant saxena
Hello sir, I have read your blog on sequencer and it is very helpful for me. but i have an doubt that can be not use TLM get/pu... Read More
Tuesday, 16 August 2016 05:44
Admin
What makes uvm_driver different from a uvm_component is that it contains a port called seq_item_port of type uvm_seq_item_pull_por... Read More
Thursday, 18 August 2016 14:49
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how to disable file name and line numbers in reports

UVM has this nice feature of being able to print the line number and file name from where a reporting task is called. This is very helpful during the early days of testbench debug, but it can soon clutter the log reports. Just imagine having the file name occupy most of the screen space, true in most projects because of the long path to a file, only to make it difficult for you to find the actual report message. Good News ! There's a way to disable this.

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Aravind Prakash
+define option is required to be given during compilation. As you might already know, the tool essentially needs to do three thing... Read More
Tuesday, 20 February 2018 17:24
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what happens when you register a component with factory ?

One of the main features of UVM is the factory mechanism, and we already know how to use `uvm_component_utils () and `uvm_object_utils () within user-defined component and object classes. It's a way of registering our new component with the factory so that we can request the factory to return an object of some other type later on via type_id::create () method. Let's see what happens behind the scene when the code is elaborated and compiled for the example that follows.

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Ratiranjan Senapati
Thanks a lot Aravind. Thanks for all your easy explanations. Helped a lot. Please keep it up ... Read More
Saturday, 08 October 2016 00:56
Rupam Kumari
Thanks for all your easy explanations. It helped me alot.
Monday, 11 September 2017 23:24
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how to turn an agent from active to passive ?

An agent is a hierarchical block which puts together other verification components that are dealing with a specific DUT interface. It usually contains a sequencer to generate data transactions, a driver to drive these transactions to the DUT, and a monitor that sits on the interface and tries to capture the pin wiggling that happens on the DUT interface. So, in a typical UVM environment there'll be multiple agents connected to various interfaces of the DUT. Sometimes, we do not want to drive anything to the DUT, but simply monitor the data produced by DUT. It would be nice to have a feature to turn the sequencer and driver of an agent ON and OFF when required.

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how to set a timeout value for simulations ?

There are ocassions when some components in the testbench keep running forever and cause the simulation to hang. Another case is when performing SoC level C tests, where you could have written a while (1) code expecting an interrupt to cause the loop to break but, instead not get the interrupt at all. Not a good place to be in, especially if you tried running it in your local machine instead of an LSF farm. Let's look at what UVM has to offer to get around this.

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how run_test( ) starts the simulation ?

Tests can be run in a UVM environment by either specifying the testname as an argument to run_test() or as a command-line argument using +UVM_TESTNAME="[test_name]". This can be considered an entry point to how UVM starts each component, configures and runs a simulation. There are a set of UVM core services within the structure, capable of providing instances to the factory and the root object. We'll see how the general flow looks like in the short explanation that follows.

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Chaitanya Kshirsagar
run_test() will start executing phsese, but how function new() in components and object get executed?
Thursday, 24 November 2016 22:30
Aravind Prakash
function new() is a class constructor and will always be executed when an object of that class is created. In UVM, objects are nor... Read More
Friday, 25 November 2016 06:10
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System Use Cases

As you might already know, modern SoC chips integrate many IPs and peripheral blocks which might be grouped together to form certain sub-systems. For example, a camera subsystem might capture signals from a device placed outside via MIPI CSI2 interface, process it using a graphic engine, and an internal DMA could send the processed data to some location in memory. Since a sub-system contains multiple IPs/peripherals, we will have to write vectors to test the basic functionalities of each block. Taking the example above, we want to know if all the MIPI lanes have been exercised, or if the graphic engine has had some kind of transaction to all the modules connected to it.

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SimVision Video Series

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Aravind Prakash
Really useful. Thanks for sharing !
Thursday, 24 September 2015 13:54
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Code Unreachability Analysis

Coverage metrics are widely used in SV/UVM verification to improve quality of the test suite and estimate the effort required to finish the verification task. They indicate how much of the design code has been exercised by existing set of tests, and provide an idea of how to write future tests that can target certain coverage holes. You can perform a code and functional coverage analysis after every regression to identify how many tests should be developed in order to target specific features of the design. Many times you'll find that in spite of trying every combination of input stimuli, there are certain pieces of code that simply does not get hit or exercised in simulation. You might have stumbled onto something called as unreachable code or dead code. As the name implies, it is part of the source code of a program or RTL that can never be executed because there is no control path to the code. Dead code can also be a piece of code that may be executed but does produce any effect on the output.

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Aravind Prakash
You may call it dead code, but in the proper sense it's not. Part of the code is unreachable only when you tie the control signal ... Read More
Wednesday, 09 March 2016 06:33
Jose Luis Cueva
Hi Aravind This works to find Unreachable FSM states ? Thanks
Tuesday, 16 May 2017 10:10
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Closed Loop verification

Recently, I had the opportunity to verify a compression algorithm block that went into one of the IP's that was being developed in-house. There were two blocks involved in which the first one writes data into a memory buffer using a compression algorithm, and the second module reads the data to decompress them on the fly, perform some operations and send the processed data to some other block in the SoC subsystem. The purpose is to verify the decompression part of the whole data flow, and the best way to do that is described in the next section.

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Verification

What is verification ?

Functional verification is the process of verifying that the logic design conforms to specification. For example, if the design is a simple 4-bit counter, functionally speaking, the counter should count from 0000 to 1111 and roll back to 0000. Verification is the task of verifying that the counter "does what it is supposed to do" - count from 0000 to 1111. If the design has some fault, and the count stops at 1100, then there's a bug in the design, which needs to be corrected. As you can see, this will make or break the design. In modern computer chips, it is very important to perform functional verification before the chip is sent for production. You wouldn't want to buy a product which contains a chip that doesn't work right ?

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C to Object Code

ARM based SoC's are very common these days in the mobile/tablet market space and other consumer electronics. In a SoC verification environment, C tests are written to exercise data transactions across various IPs in the system. C tests are converted to object code following the procedure described on this page. The object code is then loaded into memory models for the processor to execute. So, let's try to learn how a C program stored in hard disk is transformed into a program executed on a processor. There are basically four logical steps/phases that you need to be aware of.

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What is SoC verification ?

These days, SoCs are assembled by a lot of in-house and third party IP's. Integration of many processor cores and IP's is a challenging task. It is even more challenging to verify the various scenarios that comes with such complex designs. It has become essential to perform a hardware-software co-verification to cover functionalities presented by both hardware and software structures.

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Mangali BalaRaju
can u please share more information regarding Soc?? thank you.
Monday, 31 July 2017 22:15
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How to play in EDA Playground

EDA Playground is a nice online website to run simulations. So, how do you "play" in that ground ? Let me give you a quick tutorial on how to use that site, and you can simply copy-paste all the code examples within ChipVerify into the playground and run simulations. Hmm, that sounds easy doesn't it ?

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How to start block level verification

Block level verification typically requires a block level verification environment around the design and it becomes important to analyze the IO pins of the DUT. Analysis of the inputs and outputs also give some idea of the design characteristics and helps us to gain a first hand impression of the...
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