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how to randomize selected variables only

how to randomize selected variables only

Constrained randomization is a powerful feature of System Verilog that are generally applied to members of class objects which can be later extended, inherited and overridden. Sometimes we do not need the full blown feature set provided by classes to perform simple variable randomizations and would probably hesitate to create a class structure just to hold such variables. A simpler mechanism to randomize data that do not belong to a class is provided by the scope randomization function std::randomize().

Use of this function enables users to randomize data in the current scope without having to define a separate class structure. The good part is that it functions the same way as a class randomization method and also provides the facility to add inline constraints when calling the randomize() method. The variables required to be randomized are provided as arguments to the function.

  std::randomize ([var1, var2, ...]);
  std::randomize ([var1, var2, ...]) with { [constraint 1];
                                            [constraint 2];
                                            [constraint n]; };
    // std scope is optional                                            
  randomize ([var1, var2, ...]);

Let's look at a quick example of how it can be used.

module tb;
  bit [3:0]  mode;
  bit [3:0]  hist;
  bit       auto;
  initial begin
    std::randomize (mode);
    $display ("mode=0x%0h", mode);
    for (int i=0; i < 5; i++) begin
      randomize (mode, hist) with { mode dist {[0:3]:/40, [4:15]:/60};
                                    if (mode < 3) {
                                       hist inside {[3:9]}; 
                                    } else {
                                       hist inside {[13:15]};
      $display ("mode=0x%0h hist=0x%0h", mode, hist);
Simulation Output
ncsim> run
mode=0xc hist=0xe
mode=0xb hist=0xe
mode=0x1 hist=0x9
mode=0x1 hist=0x3
mode=0x2 hist=0x4
ncsim: *W,RNQUIE: Simulation is complete.
Uniquely constrain variables
about the let construct in System Verilog ?

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