The one thing that verification engineers spend most of their time on is debug. The most traditional way of debugging any problem is by sifting through logfiles to understand exactly what went wrong in a simulation. A lot of things can cause the testbench to break and the test to fail, and the logfiles can only help if you put intelligent display messages in them.
There are times when a signal within the design has to be probed or monitored for certain tasks in the testbench. Typically these are accessed via hierarchical references and tend to break when the same code is ported to different projects because of changes in design hierarchy. UVM has a set of DPI implementation tasks for backdoor accesses that has a similar effect and achieves much better code reusability.
Object oriented programming has a feature called inheritance that allows child classes to inherit members from its parent class without having to redeclare them in the child class. It's a great way to reuse existing code, and to make changes to testbenches without touching the base class structure. A
covergroup is a System Verilog keyword that allows the user to declare and define the variables to be sampled for functional coverage. In this post, I'll just share what simulation results tell us about how inherited covergroups behave and how their coverage numbers are affected.