SystemVerilog Loops - when and where to use

Loooooops. A very powerful tool. SystemVerilog has many different types of loops that can be used in a variety of ways. Using the correct loop type in the correct context helps in readability, maintenance, and shorter code. Here are a few tips to know when to use what type of loop in SystemVerilog.

Continue reading
  749 Hits
  0 Comments

Power of SystemVerilog Constraints

SystemVerilog constraints are pretty amazing ! Lets see one use case where constraints are used to generate two queues of random sizes with unique values. Let us assume total number of elements in each queue should be less than or equal to 10.

Continue reading
  981 Hits
  0 Comments

Overriding covergroups

In a previous post, we saw that covergroups are also inherited by child classes and the result of sample() on coverage of both base and child classes. Although we can keep building new covergroups in each derived child class, it would be worth to explore if the same covergroup can be overridden with a new set of coverpoints and bins in the child class.

Continue reading
  2738 Hits
  0 Comments

Using a custom sample function for functional coverage

The first way to sample covergroups is to specify an event like clock edge or an event handle that can be triggered from elsewhere in the testbench. The second way to sample covergroups is to explicitly call sample() at places where we want the variables to be sampled. The first method is usually preferred for repetitive sampling at regular event triggers. For example, we can sample the variables on every positive edge of the clock or whenever an event called "interrupt" happens. The best way to sample values at a set of specific places in the testbench is to call sample() method as required.

Continue reading
  40324 Hits
  0 Comments

Inheritance of covergroups

Object oriented programming has a feature called inheritance that allows child classes to inherit members from its parent class without having to redeclare them in the child class. It's a great way to reuse existing code, and to make changes to testbenches without touching the base class structure. A covergroup is a System Verilog keyword that allows the user to declare and define the variables to be sampled for functional coverage. In this post, I'll just share what simulation results tell us about how inherited covergroups behave and how their coverage numbers are affected.

Continue reading
Recent Comments
Admin
Thanks for noting that, the code has been corrected.
Thursday, 15 November 2018 19:50
  2183 Hits
  3 Comments

You consent to our cookies if you continue to use our website. To know more about cookies, see our privacy policy. I accept cookies from this site.

Agree