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Practical example of polymorphism in UVM

UVM factory mechanism makes the testbench more flexible and re-usable by allowing components to be overriden via the type_id::create() method. The idea is that at run-time, an object of the overridden data-type will be returned instead of the original. However, it might give a compilation error when a member of the new sub-class component is being accessed in the new environment unless properly casted. This post will describe the scenario and how to overcome the error by casting.

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RAKESH BABU Rakesh.Mla48
Can anyone provide me the edaplayground link for the above code.
Thursday, 15 August 2019 07:35
Admin
Have added a link to the code in edaplayground.
Monday, 19 August 2019 12:38
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Save time on re-compilation of the TB with an external configuration file

The testbench I was working on took quite some time to compile, elaborate and output an executable file. The design is an interconnect that has mappings from different masters to various slaves and has service registers within it accessible by specific masters. There were a block of registers for each master that would control how the transactions from the master would behave, and this required writing a lot of sequences to configure and simulate different configurations for each register. I wanted a better way to run and test a particular register set configuration without re-compiling the entire testbench and design.

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Closed Loop verification

Recently, I had the opportunity to verify a compression algorithm block that went into one of the IP's that was being developed in-house. There were two blocks involved in which the first one writes data into a memory buffer using a compression algorithm, and the second module reads the data to decompress them on the fly, perform some operations and send the processed data to some other block in the SoC subsystem. The purpose is to verify the decompression part of the whole data flow, and the best way to do that is described in the next section.

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Verification of registers

Hardware behavior is made more configurable through control registers, and the verification of these registers has become one of the primary items in the to-do list of any design. It is quite pointless to test any other feature of a design if we cannot access/modify its register bits to change any of its functionality. Registers are typically accessed using low-bandwidth bus protocols like AMBA Advanced Peripehral Bus, IBM On-Chip Peripheral Bus or something similar developed in-house by a semiconductor firm. It's because of these registers that software can exercise greater control on the overall behavior of the chip, and most design specifications have a number of pages detailing the functionalities of each bit of every register.

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Technical Resource

White papers published by EDA vendors are a really good source of information for better techniques to using languages and their tools. From Simulation to Emulation – A Fully Reusable UVM Framework Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation Lauro Rizzatti Explains Hardware Emulation’s Appeal Using Digital Verification...
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How to play in EDA Playground

EDA Playground is a nice online website to run simulations. So, how do you "play" in that ground ? Let me give you a quick tutorial on how to use that site, and you can simply copy-paste all the code examples within ChipVerify into the playground and run simulations. Hmm, that sounds easy doesn't it ?

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How to start block level verification

Block level verification typically requires a block level verification environment around the design and it becomes important to analyze the IO pins of the DUT. Analysis of the inputs and outputs also give some idea of the design characteristics and helps us to gain a first hand impression of the...
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