about the let construct in System Verilog ?
Many a time I have written functions that end up having only a single line of code in it and wished for a better alternative. System Verilog (1800-2009) has a construct called
let that defines a template expression that can be used for customization and text replacement.
let construct is supposed to be safer since it has a local scope and will not interfere with the global compiler directives. It can also be used as shortcuts for identifiers and expressions.
package my_expressions; let sum (a, b) = a + b; let max (a, b) = (a > b) ? a : b; endpackage module tb; import my_expressions::*; bit [7:0] a, b; initial begin a = $random; b = $random; $display ("a=%0d b=%0d", a, b); $display ("sum = %0d", sum(a, b)); $display ("Max = %0d", max(a, b)); end endmoduleSimulation Output
ncsim> run a=36 b=129 sum = 165 Max = 129 ncsim: *W,RNQUIE: Simulation is complete.