What is `timescale?
The `timescale directive is used to set the time units and precision for a design. It specifies the time scale used in the simulation and the unit of time for delays and times associated with signal assignments and other operations.
`timescale timeunit/precision
Read more on Verilog Timescale.
Why can't program blocks have an always block in them ?
An always block is a concurrent process that runs forever and gets triggered based on changes to signals in the sensitivity list. A program block is intended to be a testcase that applies stimulus to the DUT and finish at some point in time. Having an always block will stall the program from coming to an end and hence it doesn't make sense to include it in a program block.
What is the difference between logic and bit in SystemVerilog?
In SystemVerilog, a bit is a single binary digit that can have a value of 0 or 1, while logic is a data type used for representing a single wire or net that can have multiple states such as 0, 1, Z (high-impedance), X (unknown), or L (weakly driven low) and H (weakly driven high).
Read more on SystemVerilog Data Types.
Write pseudo code for implementing an AHB-Lite driver.
The main point in writing an AHB driver is to realize that its a pipelined protocol and hence address phase of the next transaction should be active when the data phase of current transaction is on going. This is done by starting the same task twice in a fork join.
How can we access a DUT signal in a component or sequence ?
Interface signals can be accessed via a virtual interface handle that points to the actual physical interface. Signals within the DUT can be accessed directly by providing a hierarchical RTL path to uvm_hdl_* functions such as.
uvm_hdl_force("top.eatable.fruits.apple.slice", 2);
uvm_hdl_deposit("top.eatable.fruits.apple.slice", 3);
uvm_hdl_read("top.eatable.fruits.apple.slice", rdata);
