Expression coverage is a type of code coverage that measures the percentage of Boolean expressions executed during the simulation. Here's an example of expression coverage RTL code:
Statement coverage is a type of code coverage that measures the percentage of code statements executed during the simulation. Here's an example of statement coverage RTL code:
Block coverage is a type of code coverage that measures the percentage of basic blocks executed during the simulation. A basic block is a continuous sequence of code statements with a single point of entry and a single point of exit.
Code coverage is a crucial component of verification, and it is used to ensure that the design-under-test (DUT) is properly tested. Code coverage helps to identify untested or under-tested parts of the design, which may contain bugs or errors that could impact the functionality of the design.
Constraint Random Verification (CRV) is a technique for generating randomized test cases with specific constraints to ensure that the generated input stimuli meet certain design requirements.
In CRV, a set of constraints that capture the requirements of the design, such as data ranges, timing requirements, and interface protocols are defined. The testbench then generates a set of input stimuli that satisfies these constraints. The generated test cases can then be used to verify the design's functionality and performance.
CRV is a popular verification technique because it can generate a large number of randomized test cases that cover a wide range of scenarios. By using CRV, a verification engineer can quickly identify potential design bugs that may not be found using other verification techniques.
