Assertion Based Verification (ABV) is a technique in which assertions are used as the primary means of verifying the correctness of a digital design. Assertions are statements that describe a condition that must always be true within a design, and are typically written in a hardware description language such as SystemVerilog or VHDL.
The basic idea behind ABV is to use a combination of functional and formal verification techniques to verify that the design meets its functional requirements. SystemVerilog Assertions are used to define the expected behavior of the design, and formal verification techniques are used to check that the design satisfies these assertions under all possible conditions.
Assertion-based coverage is a method of measuring the quality of functional verification of digital designs using formal verification techniques. It involves writing assertions, which are formal specifications of the expected behavior of the design, and then analyzing the coverage of those assertions over the design.
Assertion-based coverage can help to ensure that all possible corner cases and error conditions have been tested, and that the design behaves correctly under all expected conditions. It can also help to identify gaps in the verification plan and improve the overall quality of the design.
A verification plan is a comprehensive document that outlines the entire verification process for a particular design or system. It specifies the verification objectives, the verification environment, the verification strategy, the methodology to be used, the metrics to be collected, and the criteria for completion.
The verification plan also defines the verification tasks to be performed and their priorities, the tools to be used, the schedules and milestones, and the resources required. A verification plan serves as a guide for the verification team and helps ensure that the verification process is complete, consistent, and effective.