What are all different applications of FIFO?

FIFOs (First-In-First-Out) are used in a wide range of applications where data needs to be buffered or stored temporarily. Some of the most common applications of FIFOs include:

Read more: Verilog Interview Set 9

Give the code for a mod-3 counter

A modulo-3 counter has 3 states (0, 1, 2) and requires 2³ number of flip-flops.

module cntr_mod3 (input clk, rstn, output reg [1:0] out);
  always @(posedge clk) begin
    if (!rstn)
      out <= 0;
    else 
      if (&out)
        out <= 0;
      else
      	out <= out + 1;
  end 
endmodule

Read more: Verilog Interview Set 8

Difference between $stop and $finish.

$stop is used to suspend the simulation at the point where it is called, simulator license is not released and still runs as a process in host operating system. User has to restart it, typically by manually resuming the simulation from the paused point.

$finish immediately terminates the simulation process and passes control back to the operating system, and license is released because simulation has exited.

$stop is useful for debugging and inspection of intermediate results in the design, allowing designers to examine signals, waveforms, or variables at a specific point in execution, while $finish is used at the end of the simulation, indicating that the design has completed its operation.

Design frequency/2 circuit using D flip flop

A frequency divider by 2 can be designed using a D flip-flop as follows:

    _________________
   |     ________    |
   |    |        |   |
   '--->|D     Q'|---'
        |        |
        |      Q |---- clk/2
        |___^____|
            |
 clk _______|    

The input clock signal Clk is connected to the D input of the D flip-flop. The output of the flip-flop, Q, is connected back to the D input through an inverter to create a divide-by-2 circuit.

1. When the clock rises from low to high, the D flip-flop captures the value of the D input and outputs it on Q.
2. At the same time, the inverted output Q' feeds it back to the D input.
3. Thus, the output Q changes state on every positive edge of the clock, resulting in a frequency that is half of the input frequency.

Note that the input clock signal should have a duty cycle close to 50% to ensure reliable operation of the flip-flop. It is also important to ensure that the setup and hold times of the flip-flop are met to avoid timing errors.

What is $random in Verilog ?

$random is a system task that generates a new 32-bit random integer on every call with a seed value of 0 by default. The optional seed value is used to specify the starting point for the random number generator, and if specified, $random generates the same sequence of random numbers every time it is called with the same seed value. It has the following syntax:

$random(seed);

What is the default value of wire and reg?

In Verilog, the default value of an uninitialized wire is 'z' or high-impedance and the default value of an uninitialized reg is 'x' or unknown. Read more on Verilog Data Types.

Difference between inter and intra assignment delay.

An intra-assignment delay specifies a delay that occurs within an assignment statement. It is specified using the # delay operator immediately following the driver in the assignment statement.

assign #5 a = b;

An inter-assignment delay specifies the delay between assignments to a signal. It is specified using the @(delay) or wait (delay) constructs.

initial
begin
    @(posedge clk) // This waits for a positive clock edge with a delay of 1 unit
    a = b;
    #2          // This introduces an inter-assignment delay of 2 time units
    a = c;
end

Read more on Verilog Inter and Intra Assignment Delay.

Illustrate how the infinite loops get created in the looping constructs like while and for.

Infinite loops occur in programming when a loop does not have a condition to stop the iteration. Let's take a look at how infinite loops can get created in various looping constructs.

reg over;

initial begin
	over = 0;

	while (!over) begin
		#10 $display("[%0t] In Loop", $time);
	end
end

The while loop will only exit if some other process changes over to 1, and it will run forever if this does not happen.

Here is another example with for loop which will run forever because of a width mismatch in the looping variable. The looping variable i goes from 0 to 7, wraps back to 0, counts up again and never reach the exit loop condition.

reg [2:0] i;

initial begin

	for (i = 0; i < 16; i = i+1) begin
		$display("[%0t] i = %0d", i);                       	
	end                       
end

Illustrate the side-effects of a function return type without a range.

If the range of the function return type is not specified, Verilog assumes it to be a 1 bit scalar value. There would not be any compilation errors but it will result in a functional error.

module tb;

	// Should have been function [3:0] add(input [31:0] a, b);
	// Returns 1 bit value by default
  	function add(input [3:0] a, b); 	
    	return a + b;
  	endfunction

	initial begin
		$display("Sum = %0d", add(4, 5)); 	// Returns 1
	end
endmodule

Read more on Verilog Functions.

What is #0 in Verilog and its usage?

In Verilog, #0 is a delay specifier that represents zero time delay. It is processed after all active events at the current simulation time have been processed, and its usage is generally not recommended. Like all delays, it is not synthesizable either in designs.

module tb;
	reg [3:0] x;

	initial begin
      $monitor("[%0t] x = %0d", $time, x);

		x = 0;		
		#10 x = 10;
	end

	initial begin
		#10;
		#0 x = 15;   
	end	
endmodule

In the above code, the #0 delay will make the variable x get value 15 at the end of 10 time units.

How to generate two different clocks in testbench ?

To generate two different clocks in a testbench, you can use two different initial or always blocks to toggle the two clock signals. Here's an example Verilog code for generating two clock signals with different frequencies using initial blocks:

module tb;
  
  reg clk1;
  reg clk2;

  initial begin
    clk1 = 1'b0;
    forever #10 clk1 = ~clk1; // Generate a clock with 50% duty cycle and 100ns frequency
  end

  initial begin
    clk2 = 1'b0;
    forever #5 clk2 = ~clk2; // Generate a clock with 50% duty cycle and 50ns frequency
  end
  
  // Rest of the testbench code  
endmodule

In this code, two initial blocks are used to generate two clock signals, clk1 and clk2 . The forever loops in each block toggle the clock signal at a specific frequency using the `#` delay operator. You can use these clock signals to drive different components in your design or to test the asynchronous behavior of your design.

Implement flip-flop using 2:1 MUX

A flip-flop can be implemented using a 2:1 MUX (multiplexer). Here's how you can implement a D flip-flop using a 2:1 MUX in Verilog:

module dff_using_mux(input d, clk, output q);
  wire out1;
  
  assign out1 = ~clk ? d  : out1;
  assign q    =  clk ? q  : out1;
  
endmodule

What are the main data types in Verilog ?

In Verilog, there are several data types that can be used to represent different types of data. The main data types in Verilog include:

• Wire: A wire is used for simple connectivity between Verilog modules. It represents a net that can only have one driver and will be used as an output from one module and input to another.
• Reg: A reg is used to represent registers or memory elements in a Verilog design. It is used to store and manipulate data within a Verilog module.
• Integer: An integer is a data type used to represent signed integers in Verilog. It has a range of -2147483648 to 2147483647.

Read more on Verilog Data Types.

Read more: Verilog Interview Set 6

Illustrate a few important considerations in Verilog simulation regressions.

Simulation regressions are a vital part of the design cycle for digital circuits. Simulation regressions involve running a wide range of tests on a circuit design to determine how it behaves under different conditions.

There are several important considerations to keep in mind when executing simulation regressions, including:

1. Test Coverage: The goal of a simulation regression is to test the circuit design thoroughly to ensure that it meets the required specifications. Therefore, test coverage is crucial to ensure that all the possible scenarios are simulated.
2. Scalability: As the design of a digital circuit becomes more complex, the number of tests required to verify its functionality increases. Therefore, it is essential to ensure that simulation regressions are scalable, and the testbench can be easily modified as per the design.
3. Debugging Capabilities: It is essential to have a comprehensive debugging capability to identify the faults encountered during simulation regression.
4. Simulation Accuracy: The accuracy of the simulation directly impacts the breadth and depth of test coverage.

Illustrate the side effect of specifying delays in assign statements.

Delays are not synthesizable and synthesis tools ignore any kind of delays specified in assignment, blocking or non-blocking procedural statements. If the functionality depends upon the presence of the delay, then a mismatch in functional simulation will be seen between the model and the synthesized netlist.

z <= #5 x; 		// #5 will be ignored
#10 z <= x;     // #10 will be ignored

Illustrate the side effects of multiple processes writing to the same variable.

Some potential side effects of multiple processes writing to the same variable include:

• Data Races: Concurrent access to the same variable without proper synchronization can lead to data races. A data race occurs when two or more processes access the same shared variable and at least one of the processes modifies the variable. This can result in unpredictable output or program crashes.
• Inconsistent Values: Multiple updates to the same variable by different processes can result in inconsistent data values. For example, one process might read the variable before another process has finished modifying it, resulting in the use of an outdated value.
• Non-Atomic Updates: Updating a shared variable is not necessarily an atomic operation, meaning that the update can require several steps to complete. If two or more processes try to update the same variable simultaneously, this can result in partial updates, corrupt data, or race conditions in simulations.
• Deadlocks: When multiple processes try to update the same variable in a circular manner, it can result in a deadlock. Deadlock is a situation where two or more processes are waiting for each other to release a resource, but neither process can make any progress.

Most of the linting and synthesis tools can detect this and throw an error.

Same variable used in two loops running simultaneously

The following code will have functional problems as the same variable is used and updated by two concurrent blocks, although it is syntactically correct.

module tb;
  	integer i; // Same variable updated by different initial blocks

  	initial begin
		for (i = 0; i < 5; i = i+1) begin
        	#5 $display("Loop#1 : i=%0d", i);
		end 
	end
                          
  	initial begin
		for (i = 0; i < 10; i = i+1) begin
        	#10 $display("Loop#2 : i=%0d", i);
		end 
	end                          
endmodule

SystemVerilog allows you to declare the variable within the for loop thereby creating two different variables with "local" scope.

module tb;  	
  	initial begin
		for (int i = 0; i < 5; i = i++) begin
        	#5 $display("Loop#1 : i=%0d", i);
		end 
	end
                          
  	initial begin
		for (int i = 0; i < 10; i = i++) begin
        	#10 $display("Loop#2 : i=%0d", i);
		end 
	end                          
endmodule

Illustrate the side effect of an implicit 1 bit wire declaration of a multi-bit port during instantiation

In hardware description languages, it is common to connect multi-bit ports between modules through wires. However, if the connection is made without explicitly declaring a wire with the correct number of bits, the language may interpret the connection as an implicit 1-bit wire. This can have unintended consequences.

For example, consider a module with a 4-bit output port that is connected to a 4-bit input port of another module. If the connection is declared as follows:

module ModuleA(
  output [3:0] out
);

ModuleB B(.in(out[3:0]));

endmodule

module ModuleB(
  input [3:0] in
);

// ...

endmodule

Then the connection between the two modules is made with an implicit 1-bit wire, which means only the least significant bit will be used in the transfer. This can cause unexpected behavior because only one bit of the 4-bit output from ModuleA will be used in ModuleB , which can lead to incorrect results.

To avoid this issue, it is important to explicitly declare the number of bits in the wire that connects the two modules, as shown below:

module ModuleA(
  output [3:0] out
);

wire [3:0] w;

assign w = out;

ModuleB B(.in(w));

endmodule

module ModuleB(
  input [3:0] in
);

// ...

endmodule

Explain what happens when width of state registers is not increased as more states gets added in a state machine.

In a state machine, the state register is used to store the current state of the machine. The number of state bits required in the register depends on the number of states in the machine. Forgetting to increase the width of state registers as more states get added in a state machine can lead to unintended consequences.

For example, if the number of state bits in the register is less than the number of states in the machine, some state bits will be lost. This truncation will cause some states to have the same encoding, resulting in incorrect behavior. This phenomenon is called state overlap. State overlap may go unnoticed during simulation or synthesis, but it can cause significant problems in hardware. It can result in incorrect operation, and in worst cases, it may cause the system to fail completely.

// BUG! If cur_state is not updated to a 4-bit variable
// there will be functional failure

logic [2:0] 	cur_state;

...
case(cur_state)
 4'b0100 : // Move into Write phase
 4'b1100 : // Move into Read phase
...

To avoid state overlap, the width of the state register should be increased as more states get added in the state machine. The number of bits required for the state register can be calculated by using the formula 2ⁿ >= number of states, where n is the number of bits in the state register.

What is the purpose of DPI ? Give an example.

DPI stands for Direct Programming Interface, and it is a feature of SystemVerilog that allows communication between the hardware design being simulated and external software applications. The purpose of DPI is to enable the hardware design being simulated to interact with software modules.

One example of the use of DPI is in co-simulation, where a hardware design is simulated alongside a software application that interacts with it. The software application could be running on a different platform or operating system, and it communicates with the hardware through the DPI interface. This allows software engineers to test their application with the hardware design in a controlled environment.

Another example of the use of DPI is for modeling user-defined protocols or interfaces. A SystemVerilog design can have modules that interact with other modules using DPI, allowing users to implement their own communication protocols or interfaces.

For instance, let's assume a SystemVerilog design has a module that performs cryptographic operations. The design can have a DPI function that interacts with software modules written in higher-level languages like Python or C, which perform data input/output (I/O) for this design. In this case, the software modules perform I/O operations such as reading inputs like cryptography keys or plaintext data from the user at runtime, which are fed to the module using the DPI interface. Once the cryptographic module completes its operation, it can return the output to the software through the same interface, allowing for efficient and flexible communication.

What is a parameter in Verilog?

In Verilog, a parameter is a named constant that is used to simplify the design by allowing commonly used values to be defined once and then used throughout the code. Parameters are defined using the parameter keyword and are typically declared at the beginning of the Verilog module.

For example, consider the following Verilog code that defines a simple NAND gate:

module nand_gate(output reg y, input a, input b);
  parameter delay = 1; // Delay value for the gate
  always @(a, b) begin
    y = ~(a & b); // NAND gate implementation
    #delay y = y; // Delay the output by the specified time 
  end
  
endmodule

In this code, the delay parameter is defined with a value of 1, which is then used to delay the output by one time unit in the always block.

Read more on Verilog Parameters.

Illustrate the side effect of not connecting all the ports during instantiation

An unconnected port in a module is called a dangling port or floating port, and unconnected input ports have high impedance and are evaluated to Z . If the input port is used in if else conditions with == operator, then it will evaluate to a logical false.

Leaving a port unconnected can lead to excessive power consumption and unwanted coupling between nearby signals. Furthermore, it may lead to timing issues, such as setup and hold time violations, which can cause incorrect data transfer or latching.

Read more on Verilog Module Instantiations.

Illustrate the side effect of leaving an input port unconnected that influences a logic to an output port.

An input port that is unconnected will have high impedance or the logic level Z in functional simulation, and synthesis tools will optimize away the logic that propagates beyond a floating input.

module X (input a, b, output c, d);
	assign c = a & b;
	assign d = a | b;
endmodule

module Y (input m, n, output o, p);

	X u_x ( .a (), 	// input is left floating
			.b (n),
			.c (o),
			.d (p));

endmodule

The above example will get synthesized such that m is not connected to any logic within the module Y and b is directly connected to d in X.