What is uvm_object ?
All components and object classes in a UVM environment are derived from
uvm_object base class. The primary role of
uvm_object class is to define a set of common utility functions like print, copy, compare and record which can be availed by any other class in a UVM testbench to save effort.
What is uvm_root ?
uvm_root is a singleton class that serves as the top-level container for all UVM components in a verification environment whose instance is called
uvm_top. It is automatically created when UVM is initialized and is available throughout the entire simulation. Users should not create any other instance of
What is SVA?
SVA or SystemVerilog Assertions provides a syntax for expressing assertions that describe the expected behavior of a design, allowing for direct verification of its correctness.
Assertions expressed using SVA can be used to verify various types of design properties, such as proper data flow, correct timing constraints, and correct synchronization between different parts of the design. SVA can be used as a standalone language or in conjunction with other formal verification techniques such as model checking and theorem proving. It is an important tool for ensuring the correctness and reliability of digital designs in VLSI and other fields.
Read more on SystemVerilog Assertions.
What is `timescale?
`timescale directive is used to set the time units and precision for a design. It specifies the time scale used in the simulation and the unit of time for delays and times associated with signal assignments and other operations.
Read more on Verilog Timescale.
Why can't program blocks have an always block in them ?
always block is a concurrent process that runs forever and gets triggered based on changes to signals in the sensitivity list. A
program block is intended to be a testcase that applies stimulus to the DUT and finish at some point in time. Having an
always block will stall the program from coming to an end and hence it doesn't make sense to include it in a program block.