Polymorphism allows the use of a variable of the base class type to hold subclass objects and to reference the methods of those subclasses directly from the superclass variable. It also allows a child class method to have a different definition than its parent class if the parent class method is virtual in nature.
Parent and Child Assignment
A class handle is just a container to hold either parent or child class objects. It is important to understand how parent class handles holding child objects and vice-versa behave in SystemVerilog.
Assign Child Class to Base Class
Taking the same example from Inheritance, we'll assign a sub/child class instance sc to a base class handle bc.
module tb;
Packet bc; // bc stands for BaseClass
ExtPacket sc; // sc stands for SubClass
initial begin
sc = new (32'hfeed_feed, 32'h1234_5678);
// Assign sub-class to base-class handle
bc = sc;
bc.display ();
sc.display ();
end
endmodule
Data that cannot be processed is quite useless, there'll always be some form of calculation required in digital circuits and computer systems. Let's look at some of the operators in Verilog that would enable synthesis tools realize appropriate hardware elements.
Verilog Arithmetic Operators
If the second operand of a division or modulus operator is zero, then the result will be X. If either operand of the power operator is real, then the result will also be real. The result will be 1 if the second operand of a power operator is 0 (a0).
| Operator | Description |
|---|---|
| a + b | a plus b |
| a - b | a minus b |
| a * b | a multiplied by b |
| a / b | a divided by b |
| a % b | a modulo b |
| a ** b | a to the power of b |
An example of how arithmetic operators are used is given below.
module des;
reg [7:0] data1;
reg [7:0] data2;
initial begin
data1 = 45;
data2 = 9;
$display ("Add + = %d", data1 + data2);
$display ("Sub - = %d", data1 - data2);
$display ("Mul * = %d", data1 * data2);
$display ("Div / = %d", data1 / data2);
$display ("Mod %% = %d", data1 % data2);
$display ("Pow ** = %d", data2 ** 2);
end
endmodule
ncsim> run Add + = 54 Sub - = 36 Mul * = 149 Div / = 5 Mod % = 0 Pow ** = 81 ncsim: *W,RNQUIE: Simulation is complete.
Verilog Relational Operators
An expression with the relational operator will result in a 1 if the expression is evaluated to be true, and 0 if it is false. If either of the operands is X or Z, then the result will be X. Relational operators have a lower precedence than arithmetic operators and all relational operators have the same precedence.
Both while and do while are looping constructs that execute the given set of statements as long as the given condition is true.
A while loop first checks if the condition is true and then executes the statements if it is true. If the condition turns out to be false, the loop ends right there.
A do while loop first executes the statements once, and then checks for the condition to be true. If the condition is true, the set of statements are executed until the condition turns out to be false. If the condition is false, the loop ends right there.
So the difference between the two is that a do while loop executes the set of statements atleast once.
Syntax
while (<condition>) begin
// Multiple statements
end
do begin
// Multiple statements
end while (<condition>);
Example #1 - while loop
module tb;
initial begin
int cnt = 0;
while (cnt < 5) begin
$display("cnt = %0d", cnt);
cnt++;
end
end
endmodule
ncsim> run cnt = 0 cnt = 1 cnt = 2 cnt = 3 cnt = 4 ncsim: *W,RNQUIE: Simulation is complete.
Example #2
module tb;
initial begin
int cnt;
while (cnt != 0) begin
$display ("cnt = %0d", cnt);
cnt++;
end
end
endmodule
ncsim> run ncsim: *W,RNQUIE: Simulation is complete.
Example #3 - do while loop
module tb;
initial begin
int cnt = 0;
do begin
$display("cnt = %0d", cnt);
cnt++;
end while (cnt < 5);
end
endmodule
ncsim> run cnt = 0 cnt = 1 cnt = 2 cnt = 3 cnt = 4 ncsim: *W,RNQUIE: Simulation is complete.
Example #3 - do while loop
module tb;
initial begin
int cnt = 0;
do begin
$display("cnt = %0d", cnt);
cnt++;
end while (cnt == 0);
end
endmodule
ncsim> run cnt = 0 ncsim: *W,RNQUIE: Simulation is complete.
SystemVerilog functions have the same characteristics as the ones in Verilog.
Functions
The primary purpose of a function is to return a value that can be used in an expression and cannot consume simulation time.
- A function cannot have time controlled statements like
@,#,fork join, orwait - A function cannot start a task since tasks are allowed to consume simulation time
Click here to refresh functions in Verilog !
ANSI-C style declaration
module tb;
// There are two ways to call the function:
initial begin
// 1. Call function and assign value to a variable, and then use variable
int s = sum(3, 4);
$display ("sum(3,4) = %0d", s);
// 2. Call function and directly use value returned
$display ("sum(5,9) = %0d", sum(5,9));
$display ("mul(3,1) = %0d", mul(3,1));
end
// This function returns value of type "byte", and accepts two
// arguments "x" and "y". A return variable of the same name as
// function is implicitly declared and hence "sum" can be directly
// assigned without having to declare a separate return variable
function byte sum (int x, int y);
sum = x + y;
endfunction
// Instead of assigning to "mul", the computed value can be returned
// using "return" keyword
function byte mul (int x, y);
return x * y;
endfunction
endmodule
As we saw in a previous article , bigger and complex designs are built by integrating multiple modules in a hierarchical manner. Modules can be instantiated within other modules and ports of these instances can be connected with other signals inside the parent module.
These port connections can be done via an ordered list or by name.
Port Connection by ordered list
One method of making the connection between the port expressions listed in a module instantiation with the signals inside the parent module is by the ordered list.
mydesign is a module instantiated with the name d0 in another module called tb_top. Ports are connected in a certain order which is determined by the position of that port in the port list of the module declaration. For example, b in the testbench is connected to y of the design simply because both are at the second position in the list of ports.
module mydesign ( input x, y, z, // x is at position 1, y at 2, x at 3 and
output o); // o is at position 4
endmodule
module tb_top;
wire [1:0] a;
wire b, c;
mydesign d0 (a[0], b, a[1], c); // a[0] is at position 1 so it is automatically connected to x
// b is at position 2 so it is automatically connected to y
// a[1] is at position 3 so it is connected to z
// c is at position 4, and hence connection is with o
endmodule
Order of ports in the design module should be known for a correct connection.
This is very inconvenient because the order might change if a new port is added to the list or when the number of ports in the design is very large.
