It's always best to get started using a very simple example, and none serves the purpose best other than "Hello World !".
// Single line comments start with double forward slash "//"
// Verilog code is always written inside modules, and each module represents a digital block with some functionality
module tb;
// Initial block is another construct typically used to initialize signal nets and variables for simulation
initial
// Verilog supports displaying signal values to the screen so that designers can debug whats wrong with their circuit
// For our purposes, we'll simply display "Hello World"
$display ("Hello World !");
endmodule
A module called tb with no input-output ports act as the top module for the simulation. The initial block starts and executes the first statement at time 0 units. $display is a Verilog system task used to display a formatted string to the console and cannot be synthesized into hardware. Its primarily used to help with testbench and design debug. In this case, the text message displayed onto the screen is "Hello World !".
ncsim> run
Hello World !
ncsim: *W,RNQUIE: Simulation is complete.
A positive edge detector will send out a pulse whenever the signal it is monitoring changes from 0 to 1 (positive edge).
Design
The idea behind a positive edge detector is to delay the original signal by one clock cycle, take its inverse and perform a logical AND with the original signal.
module pos_edge_det ( input sig, // Input signal for which positive edge has to be detected
input clk, // Input signal for clock
output pe); // Output signal that gives a pulse when a positive edge occurs
reg sig_dly; // Internal signal to store the delayed version of signal
// This always block ensures that sig_dly is exactly 1 clock behind sig
always @ (posedge clk) begin
sig_dly <= sig;
end
// Combinational logic where sig is AND with delayed, inverted version of sig
// Assign statement assigns the evaluated expression in the RHS to the internal net pe
assign pe = sig & ~sig_dly;
endmodule
The module shown above is named pos_edge_det and has two inputs and one output. The design aims to detect the positive edge of input sig, and output pe. So we expect to see a pulse on pe whenever sig changes from value 0 to 1.
The conditional if else statement is used to make a decision about whether a statement is executed.
Click here to refresh if else if in Verilog !
SystemVerilog introduced the following if else constructs for violation checks.
unique-if, unique0-if
unique-if evaluates conditions in any order and does the following :
- report an error when none of the
ifconditions match unless there is an explicitelse. - report an erorr when there is more than 1 match found in the
if elseconditions
Unlike unique-if, unique0-if does not report a violation if none of the conditions match
No else block for unique-if
module tb;
int x = 4;
initial begin
// This if else if construct is declared to be "unique"
// Error is not reported here because there is a "else"
// clause in the end which will be triggered when none of
// the conditions match
unique if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
else
$display ("x is neither 3 nor 5");
// When none of the conditions become true and there
// is no "else" clause, then an error is reported
unique if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
end
endmodule
ncsim> run x is neither 3 nor 5 ncsim: *W,NOCOND: Unique if violation: Every if clause was false. File: ./testbench.sv, line = 18, pos = 13 Scope: tb Time: 0 FS + 1 ncsim: *W,RNQUIE: Simulation is complete.
Multiple matches in unique-if
module tb;
int x = 4;
initial begin
// This if else if construct is declared to be "unique"
// When multiple if blocks match, then error is reported
unique if (x == 4)
$display ("1. x is %0d", x);
else if (x == 4)
$display ("2. x is %0d", x);
else
$display ("x is not 4");
end
endmodule
ncsim> run
1. x is 4
ncsim: *W,MCONDE: Unique if violation: Multiple true if clauses at {line=8:pos=15 and line=10:pos=13}.
File: ./testbench.sv, line = 8, pos = 15
Scope: tb
Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.
priority-if
priority-if evaluates all conditions in sequential order and a violation is reported when:
- None of the conditions are true or if there's no
elseclause to the finalifconstruct
No else clause in priority-if
module tb;
int x = 4;
initial begin
// This if else if construct is declared to be "unique"
// Error is not reported here because there is a "else"
// clause in the end which will be triggered when none of
// the conditions match
priority if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
else
$display ("x is neither 3 nor 5");
// When none of the conditions become true and there
// is no "else" clause, then an error is reported
priority if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
end
endmodule
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Priority if violation: Every if clause was false.
File: ./testbench.sv, line = 18, pos = 15
Scope: tb
Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.
Exit after first match in priority-if
module tb;
int x = 4;
initial begin
// Exits if-else block once the first match is found
priority if (x == 4)
$display ("x is %0d", x);
else if (x != 5)
$display ("x is %0d", x);
end
endmodule
ncsim> run
x is 4
ncsim: *W,RNQUIE: Simulation is complete.
Polymorphism allows the use of a variable of the base class type to hold subclass objects and to reference the methods of those subclasses directly from the superclass variable. It also allows a child class method to have a different definition than its parent class if the parent class method is virtual in nature.
Parent and Child Assignment
A class handle is just a container to hold either parent or child class objects. It is important to understand how parent class handles holding child objects and vice-versa behave in SystemVerilog.
Assign Child Class to Base Class
Taking the same example from Inheritance, we'll assign a sub/child class instance sc to a base class handle bc.
module tb;
Packet bc; // bc stands for BaseClass
ExtPacket sc; // sc stands for SubClass
initial begin
sc = new (32'hfeed_feed, 32'h1234_5678);
// Assign sub-class to base-class handle
bc = sc;
bc.display ();
sc.display ();
end
endmodule
Data that cannot be processed is quite useless, there'll always be some form of calculation required in digital circuits and computer systems. Let's look at some of the operators in Verilog that would enable synthesis tools realize appropriate hardware elements.
Verilog Arithmetic Operators
If the second operand of a division or modulus operator is zero, then the result will be X. If either operand of the power operator is real, then the result will also be real. The result will be 1 if the second operand of a power operator is 0 (a0).
| Operator | Description |
|---|---|
| a + b | a plus b |
| a - b | a minus b |
| a * b | a multiplied by b |
| a / b | a divided by b |
| a % b | a modulo b |
| a ** b | a to the power of b |
An example of how arithmetic operators are used is given below.
module des;
reg [7:0] data1;
reg [7:0] data2;
initial begin
data1 = 45;
data2 = 9;
$display ("Add + = %d", data1 + data2);
$display ("Sub - = %d", data1 - data2);
$display ("Mul * = %d", data1 * data2);
$display ("Div / = %d", data1 / data2);
$display ("Mod %% = %d", data1 % data2);
$display ("Pow ** = %d", data2 ** 2);
end
endmodule
ncsim> run Add + = 54 Sub - = 36 Mul * = 149 Div / = 5 Mod % = 0 Pow ** = 81 ncsim: *W,RNQUIE: Simulation is complete.
Verilog Relational Operators
An expression with the relational operator will result in a 1 if the expression is evaluated to be true, and 0 if it is false. If either of the operands is X or Z, then the result will be X. Relational operators have a lower precedence than arithmetic operators and all relational operators have the same precedence.
