In simple terms it's a UVM sequencer that contain handles to other sequencers. Why do we need this ? Because we plan to use virtual sequences and want to have control over all sequencers from a central place. A request type is not required here because this sequencer is generic and not limited to handle only one particular data type.

The environment shown above has an APB agent, Wishbone agent, PCIE environment and a register layer environment. Each of these components have their own sequences and the respective sequencers on which they are launched. A virtual sequencer called m_virt_seqr is instantiated to hold references to each individual sequencer. Hence a virtual sequence executing on this virtual sequencer will have access to all the sequencers in the testbench.

Example

	class my_virtual_sequencer extends uvm_sequencer;
		`uvm_component_utils (my_virtual_sequencer)
		
		function new (string name = "my_virtual_sequencer", uvm_component parent);
			super.new (name, parent);
		endfunction
		
		// Declare handles to other sequencers here
		apb_sequencer       m_apb_seqr;
		reg_sequencer       m_reg_seqr;
		wb_sequencer        m_wb_seqr;
		pcie_sequencer      m_pcie_seqr;
	endclass

Read more: UVM Virtual Sequencer

What is a UVM sequence ?

UVM sequences are made up of several data items which can be put together in different ways to create interesting scenarios. They are executed by an assigned sequencer which then sends data items to the driver. Hence, sequences make up the core stimuli of any verification plan.

Class Hierarchy

Steps to create a UVM sequence

// my_sequence is user-given name for this class that has been derived from "uvm_sequence"
class my_sequence extends uvm_sequence;
	
	// [Recommended] Makes this sequence reusable. Note that we are calling 
	// `uvm_object_utils instead of `uvm_component_utils because sequence is a uvm_transaction object
	`uvm_object_utils (my_sequence)
	
	// This is standard code for all components
    function new (string name = "my_sequence");
    	super.new (name);
    endfunction	
endclass

	// [Optional] my_sequencer is a pre-defined custom sequencer before this sequence definition
	`uvm_declare_p_sequencer (my_sequencer)

	// [Recommended] Make this task "virtual" so that child classes can override this task definition
	virtual task body ();
		// Stimulus for this sequence comes here
	endtask

Read more: UVM Sequence [uvm_sequence]

Subscribers are basically listeners of an analysis port. They subscribe to a broadcaster and receive objects whenever an item is broadcasted via the connected analysis port. A uvm_component class does not have an in-built analysis port, while a uvm_subscriber is an extended version with an analysis port named analysis_export.

Class definition

virtual class uvm_subscriber #(type T=int) extends uvm_component;
	typedef uvm_subscriber #(T) this_type;
	
	uvm_analysis_imp #(T, this_type) analysis_export;
	
	function new (string name, uvm_component parent);
		super.new (name, parent);
		analysis_export = new ("analysis_imp", this);
	endfunction
	
	pure virtual function void write (T, t);
endclass

Read more: Subscriber [uvm_subscriber]

Design

module jk_ff ( input j,
               input k,
               input clk,
               output q);

   reg q;

   always @ (posedge clk)
      case ({j,k})
         2'b00 :  q <= q;
         2'b01 :  q <= 0;
         2'b10 :  q <= 1;
         2'b11 :  q <= ~q;
      endcase
endmodule

Hardware Schematic

Testbench

module tb_jk;
   reg j;
   reg k;
   reg clk;
   
   always #5 clk = ~clk;
   
   jk_ff    jk0 ( .j(j),
                  .k(k),
                  .clk(clk),
                  .q(q));

   initial begin
      j <= 0;
      k <= 0;
      
      #5 j <= 0;
         k <= 1;
      #20 j <= 1;
          k <= 0;
      #20 j <= 1;
          k <= 1;
      #20 $finish;
   end

   initial
      $monitor ("j=%0d k=%0d q=%0d", j, k, q);
endmodule	

A D flip-flop is a sequential element that follows the input pin d at the given edge of a clock.

Design #1: With async active-low reset

module dff 	( input d,
              input rstn,
              input clk,
              output reg q);
	
	always @ (posedge clk or negedge rstn) 
       if (!rstn)
          q <= 0;
       else
          q <= d;
endmodule

Hardware Schematic

Testbench

module tb_dff;
	reg clk;
	reg d;
	reg rstn;
	reg [2:0] delay;
	
    dff  dff0 ( .d(d),
                .rsnt (rstn),
                .clk (clk),
                .q (q));
    
    // Generate clock
    always #10 clk = ~clk;
                   
    // Testcase
    initial begin
    	clk <= 0;
    	d <= 0;
    	rstn <= 0;
    	
    	#15 d <= 1;
    	#10 rstn <= 1;
    	for (int i = 0; i < 5; i=i+1) begin
    		delay = $random;
    		#(delay) d <= i;
    	end
    end
endmodule

Design #1: With sync active-low reset

module dff 	( input d,
              input rstn,
              input clk,
              output reg q);
	
	always @ (posedge clk) 
       if (!rstn)
          q <= 0;
       else
          q <= d;
endmodule

Hardware Schematic

Testbench

module tb_dff;
	reg clk;
	reg d;
	reg rstn;
	reg [2:0] delay;
	
    dff  dff0 ( .d(d),
                .rsnt (rstn),
                .clk (clk),
                .q (q));
    
    // Generate clock
    always #10 clk = ~clk;
                   
    // Testcase
    initial begin
    	clk <= 0;
    	d <= 0;
    	rstn <= 0;
    	
    	#15 d <= 1;
    	#10 rstn <= 1;
    	for (int i = 0; i < 5; i=i+1) begin
    		delay = $random;
    		#(delay) d <= i;
    	end
    end
endmodule