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SystemVerilog randcase

Sometimes we come across scenarios where we want the solver to randomly pick one out of the many statements. The keyword randcase introduces a case statement that randomly selects one of its branches. The case item expressions are positive integer values that represent the weights associated with each item. Probability of selecting an item is derived by the division of that item's weight divided by the sum of all weights.

Syntax


randcase
	item 	: 	statement;
	...
endcase

Example

The sum of all weights is 9, and hence the probability of taking the first branch is 1/9 or 11.11%, the probability of taking the second branch is 5/9 or 55.56% and the probability of taking the last branch is 3/9 or 33.33%.

Read more: SystemVerilog randcase

SystemVerilog Package

Packages provide a mechanism for storing and sharing data, methods, property, parameters that can be re-used in multiple other modules, interfaces or programs. They have explicitly named scopes that exist at the same level as the top-level module. So, all parameters and enumerations can be referenced via this scope. Putting such definitions and declarations inside a package also avoids cluttering the global namescope. Packages can then be imported into the current scope where items in that package can be used.

Note that items within packages cannot have hierarchical references to identifiers except those created within the package or made visible by the import of another package.

Example

All packages have to be enclosed within the package and endpackage keywords.


package my_pkg;
	typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } e_signal;
	typedef struct { bit [3:0] signal_id;
                     bit       active;
                     bit [1:0] timeout; 
                   } e_sig_param;
    
	function common ();
    	$display ("Called from somewhere");
   	endfunction
    
    task run ( ... );
    	...
    endtask
endpackage

Read more: SystemVerilog Package

SystemVerilog Disable Randomization

Randomization of variables in a class can be disabled using rand_mode method call.

This is very similar to the constraint_mode() method used to Disable Constraints. So a disabled random variable is treated the same as if they had not been declared rand or randc.

rand_mode can be called both as a function and task. Current state of the variable will be returned if it is called as a function.


	// Disables randomization of variable [variable_name] inside [class_object] class
	[class_object].[variable_name].rand_mode (0);   
	
	// Enables randomization of variable [variable_name] inside [class_object] class
	[class_object].[variable_name].rand_mode (1);   

Read more: SystemVerilog Disable Randomization

SystemVerilog Disable Constraints

All constraints are by default enabled and will be considered by the SystemVerilog constraint solver during randomization. A disabled constraint is not considered during randomization.

Constraints can be enabled or disabled by constraint_mode().

Syntax

constraint_mode() can be called both as a task and as a function.

When called as a task, the method does not return anything. The task is supplied with an input argument to either turn on or off the given constraint. When called as a function, the method returns the current state of the given constraint.


// Called as a task
class_obj.const_name.constraint_mode(0); 			// Turn off the constraint
class_obj.const_name.constraint_mode(1); 			// Turn on the constraint
	
// Called as a function
status = class_obj.const_name.constraint_mode(); 	// status is an int variable to hold return value

constraint_mode() is a built-in method and cannot be overriden !

Read more: SystemVerilog Disable Constraints

SystemVerilog Inline Constraints

Consider that a class already has well written constraints and there is a need to randomize the class variables with a set of different constraints decided by the user. By using the with construct, users can declare in-line constraints at the point where the randomize() method is called. These additional constraints will be considered along with the object's original constraints by the solver.

Example


class Item;
  rand bit [7:0] id;
  
  constraint c_id { id < 25; }
  
endclass

module tb;
  
  initial begin
    Item itm = new ();
    itm.randomize() with { id == 10; }; 		// In-line constraint using with construct
    $display ("Item Id = %0d", itm.id);
  end
endmodule

Read more: SystemVerilog Inline Constraints

  1. SystemVerilog pre_randomize & post_randomize
  2. SystemVerilog Associative Array
  3. SystemVerilog Dynamic Array
  4. SystemVerilog Queue
  5. SystemVerilog 'unique' and 'priority' case

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  • SystemVerilog Interview Set 6
  • UVM Singleton Object
  • UVM Component [uvm_component]
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  • UVM Root [uvm_root]
  • UVM Interview Set 4
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