Display system tasks are mainly used to display informational and debug messages to track the flow of simulation from log files and also helps to debug faster. There are different groups of display tasks and formats in which they can print values.
$write display arguments in the order they appear in the argument list.
$write does not append the newline character
$display does and can be seen from the example shown below.
module tb; initial begin $display ("This ends with a new line "); $write ("This does not,"); $write ("like this. To start new line, use newline char "); $display ("This always start on a new line !"); end endmodule
ncsim> run This ends with a new line This does not,like this. To start new line, use newline char Hi there ! ncsim: *W,RNQUIE: Simulation is complete.
$strobe prints the final values of variables at the end of the current delta time-step and has a similar format like
module tb; initial begin reg [7:0] a; reg [7:0] b; a = 8'h2D; b = 8'h2D; #10; // Wait till simulation reaches 10ns b <= a + 1; // Assign a+1 value to b $display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b); $strobe ("[$strobe] time=%0t a=0x%0h b=0x%0h", $time, a, b); #1; $display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b); $strobe ("[$strobe] time=%0t a=0x%0h b=0x%0h", $time, a, b); end endmodule
$strobe shows the final updated value of the variable b at time 10ns which is 0x2E, and
$display picks that up only in the next simulation delta at 11ns.
ncsim> run [$display] time=10 a=0x2d b=0x2d [$strobe] time=10 a=0x2d b=0x2e [$display] time=11 a=0x2d b=0x2e [$strobe] time=11 a=0x2d b=0x2e ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit
Verilog Continuous Monitors
$monitor helps to automatically print out variable or expression values whenever the variable or expression in its argument list changes. It achieves a similar effect of calling
$display after every time any of its arguments get updated.
module tb; initial begin reg [7:0] a; reg [7:0] b; a = 8'h2D; b = 8'h2D; #10; // Wait till simulation reaches 10ns b <= a + 1; // Assign a+1 value to b $monitor ("[$monitor] time=%0t a=0x%0h b=0x%0h", $time, a, b); #1 b <= 8'hA4; #5 b <= a - 8'h33; #10 b <= 8'h1; end endmodule
$monitor is like a task that is spawned to run in the background of the main thread which monitors and displays value changes of its argument variables. A new
$monitor task can be issued any number of times during simulation.
ncsim> run [$monitor] time=10 a=0x2d b=0x2e [$monitor] time=11 a=0x2d b=0xa4 [$monitor] time=16 a=0x2d b=0xfa [$monitor] time=26 a=0x2d b=0x1 ncsim: *W,RNQUIE: Simulation is complete.
Verilog Format Specifiers
In order to print variables inside display functions, appropriate format specifiers have to be given for each variable.
|%h, %H||Display in hexadecimal format|
|%d, %D||Display in decimal format|
|%b, %B||Display in binary format|
|%m, %M||Display hierarchical name|
|%s, %S||Display as a string|
|%t, %T||Display in time format|
|%f, %F||Display 'real' in a decimal format|
|%e, %E||Display 'real' in an exponential format|
module tb; initial begin reg [7:0] a; reg [39:0] str = "Hello"; time cur_time; real float_pt; a = 8'h0E; float_pt = 3.142; $display ("a = %h", a); $display ("a = %d", a); $display ("a = %b", a); $display ("str = %s", str); #200 cur_time = $time; $display ("time = %t", cur_time); $display ("float_pt = %f", float_pt); $display ("float_pt = %e", float_pt); end endmodule
ncsim> run a = 0e a = 14 a = 00001110 str = Hello time = 200 float_pt = 3.142000 float_pt = 3.142000e+00 ncsim: *W,RNQUIE: Simulation is complete.
Verilog Escape Sequences
Some characters are considered special since they stand for other display purposes like new-line, tabs and form feeds. In order to print these special characters, each occurrence of such characters have to be escaped.
|"||The " character|
|%%||The % character|
module tb; initial begin $write ("Newline character "); $display ("Tab character stop"); $display ("Escaping " %%"); /* // Compilation errors $display ("Without escaping "); // ERROR : Unterminated string $display ("Without escaping ""); // ERROR : Unterminated string */ end endmodule
ncsim> run Newline character Tab character stop Escaping " % ncsim: *W,RNQUIE: Simulation is complete.
Lexical conventions in Verilog are similar to C in the sense that it contains a stream of tokens. A lexical token may consist of one or more characters and tokens can be comments, keywords, numbers, strings or white space. All lines should be terminated by a semi-colon
Verilog is case-sensitive, so var_a and var_A are different.
There are two ways to write comments in Verilog.
- A single line comment starts with
//and tells Verilog compiler to treat everything after this point to the end of the line as a comment.
- A multiple-line comment starts with
/*and ends with
*/and cannot be nested.
However, single line comments can be nested in a multiple line comment.
// This is a single line comment integer a; // Creates an int variable called a, and treats everything to the right of // as a comment /* This is a multiple-line or block comment */ /* This is /* an invalid nested block comment */ */ /* However, // this one is okay */ // This is also okay ///////////// Still okay
Blocking assignment statements are assigned using
= and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.
module tb; reg [7:0] a, b, c, d, e; initial begin a = 8'hDA; $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c); b = 8'hF1; $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c); c = 8'h30; $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c); end initial begin d = 8'hAA; $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e); e = 8'h55; $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e); end endmodule
Note that there are two
initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first
$display is called.
ncsim> run  a=0xda b=0xx c=0xx  a=0xda b=0xf1 c=0xx  a=0xda b=0xf1 c=0x30  d=0xaa e=0xx  d=0xaa e=0x55 ncsim: *W,RNQUIE: Simulation is complete.
Before we look at more details of the Verilog language, it would be good to understand the different layers of abstraction in chip design.
The top layer is the system level architecture that defines the various sub-blocks and groups them based on functionality. For example, a processor cluster would have multiple cores, cache blocks, and cache coherence logic. All of this will be encapsulated and represented as a single block with input-output signals.
VLSI stands for Very Large Scale Integration, which is a technology used to create integrated circuits (ICs) by combining thousands or millions of transistors into a single chip. VLSI technology has revolutionized the electronics industry by enabling the production of compact, powerful and low-cost microprocessors, memory chips, digital signal processors, and other advanced electronic devices.
As of 2020, the scale of integration in VLSI technology has reached nanometer-level processes, with feature sizes on the order of 7-5 nm, allowing for the integration of billions of transistors on a single chip. The latest processors and integrated circuits are being manufactured using 7 nm and 5 nm process nodes, enabling greater performance and power efficiency.
What is an ASIC ?
An ASIC (Application-Specific Integrated Circuit) is a type of integrated circuit (IC) that is designed to perform a specific task or function. It is customized for a particular application, unlike general-purpose ICs such as microprocessors and memory chips.
ASICs are typically used in high-performance applications where specific processing requirements need to be met, such as in networking, telecommunications, and consumer electronics. ASICs are designed and manufactured for a specific customer or application and can include digital, analog, and mixed-signal components on a single chip.
Chip Design Flow
A typical design flow follows a structure shown below and can be broken down into multiple steps. Some of these phases happen in parallel and some sequentially. We'll take a look at how a typical project design cycle looks like in the industry today.
A customer of a semiconductor firm is typically some other company who plans to use the chip in their systems or end products. So, requirements of the customer also play an important role in deciding how the chip should be designed. Naturally, the first step would be to collect the requirements, estimate the market value of the end product, and evaluate the number of resources required to do the project.