What are the different phases in UVM ?
The main phases in UVM are :
- build_phase
- connect_phase
- end_of_elaboration_phase
- start_of_simulation_phase
- run_phase
- extract_phase
- check_phase
- report_phase
- final_phase
Read more in UVM Phases.
What is a UVM RAL model ? Why is it required ?
RAL is short for Register Abstraction Layer. It is a set of base classes that can be used to create register models to mimic the register contents in a design. It is much easier to write and read from the design using a register model than sending a bus transaction for every read and write. Also the register model stores the current state of the design in a local copy called as a mirrored value. Read more in Register Layer.
Write a small function to push 10 unique values from 0 to 50 into a queue.
function random();
bit [7:0] array[$];
for (int i = 0; i 10; i++) begin
int num;
std::randomize(num) with { num inside {[0:50]};
!(num inside {array};
};
array.push_back(num);
end
endfunction
In Verilog, conditional statements are used to control the flow of execution based on certain conditions. There are several types of conditional statements in Verilog listed below.
Conditional Operator
<variable> = <condition> ? <expression_1> : <expression_2>;
The conditional operator allows you to assign a value to a variable based on a condition. If the condition is true, expression_1 is assigned to the variable. Otherwise, expression_2 is assigned.
Static cast is a SystemVerilog feature that allows converting an expression from one data type to another at compile time.
Syntax
'(value or variable or expression)
Properties
Here are some of the properties of static cast in SystemVerilog:
