Ports are a set of signals that act as inputs and outputs to a particular module and are the primary way of communicating with it. Consider a module as a fabricated chip placed on a PCB, and it becomes obvious that the only way to make the chip work is by sending in signals via its pins. Similarly in the Verilog world, ports are used to send and receive signals from the module.
input [net_type] [range] list_of_names; inout [net_type] [range] list_of_names; output [net_type] [range] list_of_names; output [var_type] [range] list_of_names;
It is illegal to use the same name for multiple ports.
input aport; // First declaration - valid input aport; // Error - already declared output aport; // Error - already declared
signed attribute can be attached to a port declaration or a net/reg declaration or both. If either the net/reg declaration has a
signed attribute, then the other shall also be considered signed. Implicit nets are by default unsigned.
module ( input signed a, b, output c); wire a, b; // a, b are signed from port declaration reg signed c; // c is signed from reg declaration endmodule
A module declaration can list the names of ports related to the module and direction of those ports can be defined later inside the body of the module.
module test (a, b); input [7:0] a; // inputs a,b are unsigned input [7:0] b; endmodule module test (a, b); input signed [7:0] a; // a is signed input [7:0] b; // b is unsigned wire signed [7:0] b; // b is explicitly made wire and signed endmodule module test (a, b, c); input [7:0] a, b; output [7:0] c; // By default c is of type wire reg [7:0] c; // c is now of type reg endmodule
If a port declaration includes a net or variable type, then that port is considered to be completely declared. It is illegal to redeclare the same port in a net or variable type declaration. If the port declaration does not include a net or variable type, then the port can be declared in a net or variable type declaration again.
module test ( input [7:0] a, output [7:0] e ); // a, e are implicitly declared of type wire endmodule module test ( input [7:0] a, output reg [7:0] e); // e is explicitly declared of type reg endmodule module test ( input [7:0] a, output [7:0] e); wire signed [7:0] a; // illegal - declaration of a is already complete reg [7:0] e; // Okay - net_type was not declared before endmodule