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Parameters are constants and hence it's illegal to modify their value at runtime. It is illegal to redeclare a name already used by a net, variable or another parameter. There are two major types of parameters, module and specify and both accepts a range specification. But, they are normally made as wide as the value to be stored requires them to be and hence a range specification is not necessary.

Module parameters

Module parameters can be used to override parameter definitions within a module and this makes the module have a different set of parameters at compile time. A parameter can be modified with the defparam statement or in the module instance statement. It is a common practice to use uppercase letters as names for the parameter to make them instantly noticeable.

 
  parameter MSB = 7;                  // MSB is a parameter with a constant value 7
  parameter REAL = 4.5;               // REAL holds a real number
 
  parameter FIFO_DEPTH = 256, 
            MAX_WIDTH = 32;           // Declares two parameters
 
  parameter [7:0] f_const = 2'b3;     // value is converted to 8 bits; 8'b3
 

Now let's see a real usecase on how parameters become helpful. The module shown below uses parameters to specify the bus width, data width and the depth of FIFO within the design, and can be overriden with new values when the module is instantiated or by using defparam statements.

 
  module design_ip  ( addr,  
                      wdata,
                      write,
                      sel,
                      rdata);
 
       parameter  BUS_WIDTH    = 32, 
                  DATA_WIDTH   = 64,
                  FIFO_DEPTH   = 512;
 
       input addr;
       input wdata;
       input write;
       input sel;
       output rdata;
 
       wire [BUS_WIDTH-1:0] addr;
       wire [DATA_WIDTH-1:0] wdata;
       reg  [DATA_WIDTH-1:0] rdata;
 
       reg [7:0] fifo [FIFO_DEPTH];
 
       // Design code goes here ...
  endmodule
 

In the new ANSI style of Verilog port declaration, you may declare parameters as show below.

 
module design_ip #(parameter BUS_WIDTH=32, DATA_WIDTH=64) (input [BUS_WIDTH-1:0] addr,
                                                           ...);
 

Overriding parameters

 
  module tb;
 
      // Module instantiation override
    design_ip  #(BUS_WIDTH = 64, DATA_WIDTH = 128) d0 ( [port list]);
 
    // Use of defparam to override
    defparam d0.FIFO_DEPTH = 128;
 
    // rest of the testbench code
  endmodule
 

Specify parameters

These are primarily used for providing timing and delay values and are declared using the specparam keyword. It is allowed to be used both within the specify block and the main module body.

 
  // Use of specify block
  specify
    specparam  t_rise = 200, t_fall = 150;
    specparam  clk_to_q = 70, d_to_q = 100;
  endspecify
 
  // Within main module
  module  my_block ( ... );
     specparam  dhold = 2.0;
     specparam  ddly  = 1.5;
 
     parameter  WIDTH = 32;
  endmodule
 

Difference between specify and module parameters

Specify parameter Module parameter
Declared by specparam Declared by parameter
Can be declared inside specify block or within main module Can only be declared within the main module
May be assigned specparams and parameters May not be assigned specparams
SDF can be used to override values Instance declaration parameter values or defparam can be used to override

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