Circuits are not always built from scratch. Usually smaller components are clubbed together to form bigger ones. For example, you can create a single bit adder and connect four instances of the adder to form a 4-bit adder. This property is exploited by the feature of having modules in Verilog. Another example is the breakdown of a simple GPU into smaller components each that can be encapsulated as a module to perform a specific functionality.
module is a block of verilog code that implements a certain functionality which can be reused as a part of building something bigger or used as a standalone unit. Modules can be embedded within other modules where a higher level module can communicate with its lower level modules using their input and output ports. A module should be enclosed within
endmodule keywords. Name of the module should be given right after the
module keyword and an optional list of ports may be declared as well. Note that ports declared in the list of port declarations cannot be redeclared within the body of the module.
module name; ... endmodule module [name] ([port_list]); ... endmodule
A module is allowed to be empty, although it doesn't serve any purpose.
module des; endmodule
Another example of a simple module that represents the functionality of a TFF is given below. Typically modules are much more complex and perform a lot of computation.
module tff (input clk, t, rstn, output reg q); always @ (posedge clk) begin if (! rstn) q <= 0; else if (t) q <= ~q; else q <= q; end endmoduleTop-Level modules
Top level modules are those that are included in the source text but are not instantiated within any other modules. For example, design modules are normally instantiated within top level testbench modules so that simulation can be run by providing input stimulus. But, the testbench is not instantiated within any other module because it is a block that encapsulates everything else and hence could be the top-level module. Instantiation of a module is very similar to the concept of creation of class objects in C++.
module design ( [port_list]); ... endmodule module testbench; design d0 ( ... ); endmodule