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As discussed before, bigger and complex designs are built by integrating multiple modules in a hierarchical way. Modules are instantiated within other modules and ports can connected to each other for communication between them.

Connection by ordered list

One method of making the connection between the port expressions listed in a module instantiation is by the ordered list. mydesign is a module instantiated of name d0 within another module tb_top where ports are connected by an ordered list. Inputs x, y and z are connected to a[0], b, and a[1] respectively. Output port o is connected to the wire c in tb_top.

 
  module mydesign ( input  x, y, z,
                    output o);
 
  endmodule
 
  module tb_top;
    wire [1:0]  a;
    wire        b, c;
 
    mydesign d0  (a[0], b, a[1], c);
 
  endmodule
 

Note that the order of ports in the design module should be remembered to make the connection. This is very inconvenient as the order might change if a new port is added to the list or when the number of ports in the design is very large.

Connection by name

A better way to connect ports is to explicitly link ports on both the sides using their port names. Note that the name in the design will come first followed by the name in the instantiating module within parantheses. A compilation error will point to the line causing the problem and hence it is a common practice to keep ports in separate lines for easier debug.

 
    module tb_top;
    wire [1:0]  a;
    wire        b, c;
 
    mydesign d0  ( .x (a[0]), 
                   .y (b), 
                   .z (a[1]), 
                   .o (c));
 
  endmodule
 

Because these connections are made by name, the order in which they appear is irrelevant. Multiple module instance port connections are not allowed.

 
  module tb_top;
    mydesign d0 ( .x (a[0]),
                  .x (b),        // illegal - x is already connected to a[0]
                  .y (a[1]),
                  .z (a[1]),
                  .o (c));
  endmodule
 

Ports that are not connected to any wire in the instantiating module will have a value of high-impedance and will show up in the waveform as Z.

 
    module tb_top;
    mydesign d0 (                // x is not connected and will be Z
                  .y (a[1]),
                  .z (a[1]),
                  .o ());        // o has valid value in mydesign but since
                                 // it is not connected to c, c in tb_top will be Z
  endmodule
 

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