All procedures in Verilog are placed within one of the following blocks.
initial block is enabled at the beginning of a simulation at time 0 unit, and will be executed only once during the entire simulation. This block finishes once all the statements within the block are executed. The
initial construct need not be scheduled and executed before the always constructs. There are no limits to the number of
initial blocks that can be defined inside a module.
initial [statement] initial [statement] initial begin [multiple statements] end
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In the example shown below, data will get value 0 at time 0 units and rest of the statements are executed one by one. The initial block finishes when there are no more statments after the last line which assigns data to 8'hff at time 80 units.
initial begin data = 8'h0; #10 reset = 1; #20 enable = 1; $display ("data=0x%0h", data); data = 8'hab; #50 data = 8'ff; end
initial construct can be used to initialize testbench variables at the beginning of a simulation.
always block repeats continuously throughout the duration of a simulation and is best used with some form of a timing control. If there are no timing control statments within an always block, the simulation will hang because of a zero-delay infinite loop !
always clk = ~clk;
By adding a delay statement within the
always construct, advancement of simulation time can be achieved.
always #10 clk = ~clk;
Here is an example of a D-FF in which the logic block becomes active on the positive edge of clk.
always @ (posedge clk) begin if (!resetn) q <= 0; else q <= d; end