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It's always best to get started using a very simple example, and none serves the purpose best other than "Hello World !".

 
  // Single line comments start with //
  // Verilog code is always written inside modules, and each module represents a digital block with some functionality
  module tb;
 
      // Initial block is another construct typically used to initialize signal nets and variables for simulation
    initial
      // Verilog supports displaying signal values to the screen so that designers can debug whats wrong with their circuit
      // For our purposes, we'll simply display "Hello World" 
      $display ("Hello World !");
  endmodule
 

We have a module called tb with no ports and act as the top module for the simulation. The initial block starts at time 0 units, and the first statement will be executed. $display is a Verilog system task used to display a formatted string on to the screen, and cannot be converted into hardware. Hence it's primary use is to help aid in testbench and design debug. In this case, the text message displayed onto the screen is Hello World !.

All verilog designs are meant to undergo a simulation and verification routine before it gets finalized for the next stage in a chip design flow. Modelsim is a simulation tool from Mentor Graphics with which we can simulate verilog code and check for its behavior. The console output for our verilog code is given below.

Simulation Log
ncsim> run
Hello World !
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

Click on the video below to see how you can install Modelsim and start learning Verilog !

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