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Design

 
module fulladd (  input [3:0] a,
                  input [3:0] b,
                  input c_in,
                  output c_out,
                  output [3:0] sum);
 
   assign {c_out, sum} = a + b + c_in;
endmodule
 

Testbench

 
module tb_fulladd;
   reg [3:0] a;
   reg [3:0] b;
   reg c_in;
   wire [3:0] sum;
   integer i;
 
   fulladd  fa0 ( .a (a),
                  .b (b),
                  .c_in (c_in),
                  .c_out (c_out),
                  .sum (sum));
 
   initial begin
      a <= 4'h4;
      b <= 4'h3;
      c_in <= 1;
 
      for (i = 0; i < 10; i=i+1) begin
         #10 a <= i;
             b <= i + 3;
         if (i==2)
            c_in <= 0;
      end
   end
endmodule
 

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