Hardware behavior cannot be implemented without conditional statements and other ways to control the flow of logic. Verilog has a set of control flow blocks and mechanisms to achieve the same.
This conditional statement is used to make a decision about whether certain statements should be executed or not. This is very similar to the
if-else-if statements in C. If the expression evaluates to true, then the first statement will be executed. If the expression evaluates to false and if an
else part exists, the
else part will be executed. The
else part of an if-else is optional and can cause a confusion if an
else is omitted in a nested if sequence. To avoid this confusion, it's easier to always associate the else to the previous if that lacks an else. Another way is to enclose statements within a
if (expression) [statement] if (expression) [statement] else [statement] if (expression) begin [multiple statements] end else begin [multiple statements] end if (expression) [statement] else if (expression) [statement] else [statement]
else part handles none-of-the-above or default case where none of the other conditions were satisfied.
case statement is useful to test if an expression matches one of the other expressions in the list and branches accordingly. The
default statement is optional and use of multiple default statements is illegal. The expression within parantheses will be evaluated exactly once and matched with the case item in the same order as they are listed within the
case block. If one of the case items match then the statements associated with that item will be executed and then exit the case block. If none of the case items match, then the set of statements associated with the
default item will be executed if present, else it simply exits the case block without doing anything else.
case (expression) item1 : [single statement] item2 : begin [multiple statements] end default : [statement] endcase
case statement is different from
if-else-if in two ways:
- Expressions given in a
if-elseblock are more general while in a
caseblock, a single expression is matched with multiple items
casewill provide a definitive result when there are X and Z values in an expression
Loops provide a way of executing single or multiple statements within a block one or more number of times. There are four different types of looping statements in Verilog.forever
This will continuously execute the statements within the block.
forever [statement] forever begin [multiple statements] endrepeat
This will execute statements a fixed number of times. If the expression evaluates to an X or Z, then it will be treated as zero and will not be executed at all.
repeat ([num_of_times]) begin [statements] end repeat ([num_of_times]) @ ([some_event]) begin [statements] endwhile
This will execute statements as long as an expression is true and will exit once the condition becomes false. If the condition is false from the start, statements will not be executed at all.
while (expression) begin [statements] endfor
This will control statements using a three-step process:
- Initialize a loop counter variable
- Evaluate the expression, usually involving the loop counter variable
- Increment loop counter variable so that at a later time the expression will become false and loop will exit.
for ( initial_assignment; condition; increment_variable) begin [statements] end