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Now we'll see how two components can be connected through it's port and export ports, and perform a simple data transaction using the simple_packet class object shown in the preface. In this example, componentA takes the initiative to send the packet to componentB, and componentB is configured to simply accept the data it gets from componentA.

If our component is derived from uvm_component, port information will have to be added in the class. For this example, we'll declare a blocking TLM put port in componentA. Since put_port is a class object, it has to be created using the new () function, and as you already know, the best place for that is in the build_phase() method. When data is ready to be sent, simply call the put() method.

 
class componentA extends uvm_component;
   `uvm_component_utils (componentA)
 
   // We are creating a blocking TLM put port which will accept a "simple_packet" type of data
   uvm_blocking_put_port #(simple_packet) put_port;
   simple_packet  pkt;
 
   function new (string name = "componentA", uvm_component parent= null);
      super.new (name, parent);
   endfunction
 
   virtual function void build_phase (uvm_phase phase);
      super.build_phase (phase);
      // Remember that TLM put_port is a class object and it will have to be 
      // created with new ()
      put_port = new ("put_port", this);
   endfunction
 
   virtual task run_phase (uvm_phase phase);
      // Let us generate 5 packets and send it via the TLM put port
      repeat (5) begin
         pkt = simple_packet::type_id::create ("pkt");
         assert(pkt.randomize ()); 
         `uvm_info ("COMPA", "Packet sent to CompB", UVM_LOW)
         pkt.print (uvm_default_line_printer);
 
         // Call the TLM put() method of put_port class and pass packet as argument
         put_port.put (pkt);
      end
   endtask
endclass
 

In componentB, we have to write the implementation of the put() method we called in componentA. We also have to create an export port to accept the data - use uvm_blocking_put_imp.

 
class componentB extends uvm_component;
   `uvm_component_utils (componentB)
 
   // Mention type of transaction, and type of class that implements the put ()
   uvm_blocking_put_imp #(simple_packet, componentB) put_export;

   function new (string name = "componentB", uvm_component parent = null);
      super.new (name, parent);
   endfunction
 
   virtual function void build_phase (uvm_phase phase);
      super.build_phase (phase);
      put_export = new ("put_export", this);
   endfunction
 
   task put (simple_packet pkt);
      // Here, we have received the packet from componentA 
      `uvm_info ("COMPB", "Packet received from CompA", UVM_LOW)
      pkt.print ();
   endtask
endclass
 

tlm-testbench-structure

Wait a second - we are not done yet, the connection between the two components are missing ! This can be easily done at the environment level, by calling the connect () method of the port in componentA.

 
class my_env extends uvm_env;
   `uvm_component_utils (my_env)
 
   componentA compA;
   componentB compB;
 
   function new (string name = "my_env", uvm_component parent = null);
      super.new (name, parent);
   endfunction
 
   virtual function void build_phase (uvm_phase phase);
      super.build_phase (phase);
      // Create an object of both components
      compA = componentA::type_id::create ("compA", this);
      compB = componentB::type_id::create ("compB", this);
   endfunction
 
   // Connection between componentA and componentB is done here
   virtual function void connect_phase (uvm_phase phase);
      compA.put_port.connect (compB.put_export);  
   endfunction
endclass
 

Watch the example !

Simulation Output

----------------------------------------------------------------
CDNS-UVM-1.1d (15.10-s004)
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
UVM_INFO @ 0: reporter [RNTST] Running test base_test...
UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
----------------------------------------------------
Name              Type                   Size  Value
----------------------------------------------------
uvm_test_top      base_test              -     @2599
  m_top_env       my_env                 -     @2665
    compA         componentA             -     @2696
      put_port    uvm_blocking_put_port  -     @2775
    compB         componentB             -     @2726
      put_export  uvm_blocking_put_imp   -     @2828
----------------------------------------------------

UVM_INFO ./tb/tlm.sv(61) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@2888) { addr: 'h2f  data: 'h64  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(89) @ 0: uvm_test_top.m_top_env.compB [COMPB] Packet received from CompA
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @2888
  addr  integral       8     'h2f
  data  integral       8     'h64
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(61) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@2911) { addr: 'hb8  data: 'h27  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(89) @ 0: uvm_test_top.m_top_env.compB [COMPB] Packet received from CompA
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @2911
  addr  integral       8     'hb8
  data  integral       8     'h27
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(61) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@2904) { addr: 'he3  data: 'h29  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(89) @ 0: uvm_test_top.m_top_env.compB [COMPB] Packet received from CompA
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @2904
  addr  integral       8     'he3
  data  integral       8     'h29
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(61) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@2915) { addr: 'h85  data: 'hbd  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(89) @ 0: uvm_test_top.m_top_env.compB [COMPB] Packet received from CompA
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @2915
  addr  integral       8     'h85
  data  integral       8     'hbd
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(61) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@2872) { addr: 'hdf  data: 'hab  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(89) @ 0: uvm_test_top.m_top_env.compB [COMPB] Packet received from CompA
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @2872
  addr  integral       8     'hdf
  data  integral       8     'hab
  rwb   integral       1     'h0
----------------------------------

--- UVM Report catcher Summary ---


Number of demoted UVM_FATAL reports  :    0
Number of demoted UVM_ERROR reports  :    0
Number of demoted UVM_WARNING reports:    0
Number of caught UVM_FATAL reports   :    0
Number of caught UVM_ERROR reports   :    0
Number of caught UVM_WARNING reports :    0

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   12
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[COMPA]     5
[COMPB]     5
[RNTST]     1
[UVMTOP]     1
Simulation complete via $finish(1) at time 0 FS + 179

That's it, we're done. Next, we'll take a look at the scenario where componentB requests for data from componentA using TLM get()

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