Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !

Let's try to make our components operate more independently by placing a TLM FIFO in between the two components. That way componentA can keep sending data, which will be stored in the FIFO, and componentB can get the data from the FIFO when it's free to do so.


GitHub

You can download/clone the code example from our repository at GitHub or Downloads page.


TestBench

We'll combine previous examples in TLM Put and TLM Get to make componentA put data into the FIFO using put() method in it's port, and componentB get data using get() method through it's export. Code remains the same as before for componentA and componentB, except that in the environment, we will now have a new TLM FIFO object as well.

 
class my_env extends uvm_env;
   `uvm_component_utils (my_env)
 
   componentA compA;
   componentB compB;
 
   // Create the UVM TLM Fifo that can accept simple_packet
   uvm_tlm_fifo #(simple_packet)    tlm_fifo;
 
   function new (string name = "my_env", uvm_component parent = null);
      super.new (name, parent);
   endfunction
 
   virtual function void build_phase (uvm_phase phase);
      super.build_phase (phase);
      // Create an object of both components
      compA = componentA::type_id::create ("compA", this);
      compB = componentB::type_id::create ("compB", this);
 
      // Create a FIFO with depth 2
      tlm_fifo = new ("uvm_tlm_fifo", this, 2);
   endfunction
 
   // Connect the ports to the export of FIFO.
   virtual function void connect_phase (uvm_phase phase);
      compA.put_port.connect (tlm_fifo.put_export);
      compB.get_port.connect (tlm_fifo.get_export);
   endfunction
 
   // Display a message when the FIFO is full
   virtual task run_phase (uvm_phase phase);
      forever begin
         #10 if (tlm_fifo.is_full ()) 
               `uvm_info ("UVM_TLM_FIFO", "Fifo is now FULL !", UVM_MEDIUM)
      end
   endtask
endclass
 
uvm-tlm-fifo

You can see that we connected both the ports in componentA/B to the exports in TLM Fifo.


Watch the example !

Simulation Output

----------------------------------------------------------------
CDNS-UVM-1.1d (15.10-s004)
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
UVM_INFO @ 0: reporter [RNTST] Running test base_test...
UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
---------------------------------------------------------
Name                   Type                   Size  Value
---------------------------------------------------------
uvm_test_top           base_test              -     @2600
  m_top_env            my_env                 -     @2666
    compA              componentA             -     @2697
      put_port         uvm_blocking_put_port  -     @3005
    compB              componentB             -     @2727
      get_port         uvm_blocking_get_port  -     @3056
    tlm_fifo           uvm_tlm_fifo #(T)      -     @2660
      get_ap           uvm_analysis_port      -     @2954
      get_peek_export  uvm_get_peek_imp       -     @2856
      put_ap           uvm_analysis_port      -     @2905
      put_export       uvm_put_imp            -     @2805
---------------------------------------------------------

UVM_INFO ./tb/tlm.sv(60) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@3136) { addr: 'h2f  data: 'h64  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(60) @ 0: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@3152) { addr: 'hb8  data: 'h27  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(131) @ 10000: uvm_test_top.m_top_env [TLMFIFO] Fifo is now FULL !
UVM_INFO ./tb/tlm.sv(91) @ 10000: uvm_test_top.m_top_env.compB [COMPB] ComponentA just gave me the packet
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @3136
  addr  integral       8     'h2f
  data  integral       8     'h64
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(60) @ 10000: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@3154) { addr: 'he3  data: 'h29  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(131) @ 20000: uvm_test_top.m_top_env [TLMFIFO] Fifo is now FULL !
UVM_INFO ./tb/tlm.sv(91) @ 20000: uvm_test_top.m_top_env.compB [COMPB] ComponentA just gave me the packet
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @3152
  addr  integral       8     'hb8
  data  integral       8     'h27
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(60) @ 20000: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@3171) { addr: 'h85  data: 'hbd  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(131) @ 30000: uvm_test_top.m_top_env [TLMFIFO] Fifo is now FULL !
UVM_INFO ./tb/tlm.sv(91) @ 30000: uvm_test_top.m_top_env.compB [COMPB] ComponentA just gave me the packet
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @3154
  addr  integral       8     'he3
  data  integral       8     'h29
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(60) @ 30000: uvm_test_top.m_top_env.compA [COMPA] Packet sent to CompB
pkt: (simple_packet@3169) { addr: 'hdf  data: 'hab  rwb: 'h0  }
UVM_INFO ./tb/tlm.sv(131) @ 40000: uvm_test_top.m_top_env [TLMFIFO] Fifo is now FULL !
UVM_INFO ./tb/tlm.sv(91) @ 40000: uvm_test_top.m_top_env.compB [COMPB] ComponentA just gave me the packet
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @3171
  addr  integral       8     'h85
  data  integral       8     'hbd
  rwb   integral       1     'h0
----------------------------------
UVM_INFO ./tb/tlm.sv(91) @ 50000: uvm_test_top.m_top_env.compB [COMPB] ComponentA just gave me the packet
----------------------------------
Name    Type           Size  Value
----------------------------------
pkt     simple_packet  -     @3169
  addr  integral       8     'hdf
  data  integral       8     'hab
  rwb   integral       1     'h0
----------------------------------
UVM_INFO /pkg/cadence-incisiv-/15.10.004/i686-linux/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_objection.svh(1268) @ 50000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

--- UVM Report catcher Summary ---


Number of demoted UVM_FATAL reports  :    0
Number of demoted UVM_ERROR reports  :    0
Number of demoted UVM_WARNING reports:    0
Number of caught UVM_FATAL reports   :    0
Number of caught UVM_ERROR reports   :    0
Number of caught UVM_WARNING reports :    0

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   17
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[COMPA]     5
[COMPB]     5
[RNTST]     1
[TEST_DONE]     1
[TLMFIFO]     4
[UVMTOP]     1
Simulation complete via $finish(1) at time 50 NS + 44

Next we'll talk about how to connect components at different levels of hierarchy.

Was this article helpful ?

We use cookies to personalize content and ads, to provide social media features and to analyze our traffic. You consent to our cookies if you continue to use our website. To find out more about the cookies we use and how to delete them, see our privacy policy.

  I accept cookies from this site.
Agree
EU Cookie Directive plugin by www.channeldigital.co.uk