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What are loops ?

A loop is a piece of code that keeps executing over and over. A conditional statement is typically included in a loop so that it can terminate once the condition becomes true. If the loop runs forever, then the simulation will hang indefinitely.

Different types of looping constructs in SystemVerilog are:

  • forever
  • repeat
  • while
  • for
  • do while
  • foreach

forever

This is an infinite loop, just like while (1). Note that your simulation will hang unless you include a time delay inside the forever block to advance simulation time.

 
module tb;
 
  // This initial block has a forever loop which will "run forever"
  // Hence this block will never finish in simulation
  initial begin
    forever begin
      #5 $display ("Hello World !");
    end
  end
 
  // Because the other initial block will run forever, our simulation will hang!
  // To avoid that, we will explicity terminate simulation after 50ns using $finish
  initial 
    #50 $finish;    
endmodule
 

Note that simulation would have continued indefinitely if $finish was not called.

Simulation Log
ncsim> run
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Simulation complete via $finish(1) at time 50 NS + 0

Click to try this example in a simulator!   

repeat

Used to repeat statements in a block a certain number of times. The example shown below will display the message 5 times and continues with rest of the code.

 
module tb;
 
    // This initial block will execute a repeat statement that will run 5 times and exit
  initial begin
 
        // Repeat everything within begin end 5 times and exit "repeat" block
    repeat(5) begin
      $display ("Hello World !");
    end
  end
endmodule
 
Simulation Log
ncsim> run
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

while

You already know this if you know verilog/C. It'll repeat the block as long as the condition is true.

 
initial begin
  bit [3:0] counter;
 
  while (counter < 10) begin
    @(posedge clk);
    counter++;
  end
  $display ("Counter = %0d", counter);      // Counter = 10
end
 

for

Similar to verilog/C, this allows you to mention starting value, condition and incremental expression all on the same line.

 
initial begin
  bit [3:0] counter;
  for (counter = 2; counter < 14; counter = counter + 2) begin
    @(posedge clk);
  end
  $display ("There are %0d edges of clk", counter);
end
 

do while

This executes the code first and then checks for the condition to see if the code should be executed again.

 
module tb_top;
  bit clk;
 
  always #10 clk <= ~clk;
 
  initial begin
    bit [3:0] counter;
    do begin 
      @ (posedge clk);
      counter ++;
    end while (counter < 1);
  end
endmodule
 

foreach

This is best suited to loop through array variables, because you don't have to find the array size, set up a variable to start from 0 until array_size-1 and increment it on every iteration.

 
module tb_top;
   bit [7:0] array [8];   // Create a fixed size array
 
   initial begin
 
      // Assign a value to each location in the array
      foreach (array [index]) begin
         array[index] = index;
      end
 
      // Iterate through each location and print the value of current location
      foreach (array [index]) begin
         $display ("array[%0d] = 0x%0d", index, array[index]);
      end
   end
endmodule
 
Simulation Log
array[0] = 0x0
array[1] = 0x1
array[2] = 0x2
array[3] = 0x3
array[4] = 0x4
array[5] = 0x5
array[6] = 0x6
array[7] = 0x7

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