Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !

Featured Posts

why connect phase is bottom to top?

Driver Sequencer hadnshake hung

How can we configure a UVM Verification TB to support Hot Join?

try_next_item

How to calculate Address for the Unaligned Address in AXI Protocol?

Explain Backdoor and Front door register access in RAL ?

In UVM, Why run_phase() execute in parallel ?

Explain the difference in woring frequency and bandwidth of a device ?

Proxy objects and wrappers in UVM

How to get coverage of interface signals which are connected directly from DUT to Scoreboard??

Difference between Scoreboard and Subscriber?

Why in most of the protocols we use Active Low Reset ?

VLSI question

Data structure

Scoreboard

just uvm...

wrapper class

Can we get transaction in Functional Coverage through multiple Analysis Ports in Scoreboard ?

Not able to set password for a new profile ?

Passing virtual interface without config_db



There are no discussions available here currently
  • Page :
  • 1
  • 2
  1. Posts: 32
  2. Resolved Posts: 23
  3. Unresolved Posts: 32
  4. Latest Member: Nikhil Jadhav
Online Members

We use cookies to personalize content and ads, to provide social media features and to analyze our traffic. You consent to our cookies if you continue to use our website. To find out more about the cookies we use and how to delete them, see our privacy policy.

  I accept cookies from this site.
Agree
EU Cookie Directive plugin by www.channeldigital.co.uk