Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !

Categories

Uncategorized
  1. 1 discussion
  2. 0 subcategories
UVM
    Topics related to Universal Verification Methodology
  1. 23 discussions
  2. 0 subcategories
Forum
    Any questions/concerns related to Forum usage or Forum in general can be put in this category.
  1. 3 discussions
  2. 0 subcategories
Careers
    All career related discussions can be put in here.
  1. 1 discussion
  2. 0 subcategories
SoC
    SoC verification related topics definitely need a separate category.
  1. 3 discussions
  2. 0 subcategories
General
    Other general discussion related to either news/blog posts or events.
  1. 7 discussions
  2. 0 subcategories
EDA
    Having problems running simulations ? Any questions related to tools ? Post here.
  1. 2 discussions
  2. 0 subcategories
Compilation & Runtime Errors
  1. 1 discussion
  2. 0 subcategories

We use cookies to personalize content and ads, to provide social media features and to analyze our traffic. You consent to our cookies if you continue to use our website. To find out more about the cookies we use and how to delete them, see our privacy policy.

  I accept cookies from this site.
Agree
EU Cookie Directive plugin by www.channeldigital.co.uk