Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !
1 minute reading time (115 words)

What is SystemVerilog ?

What is SystemVerilog ?

It's a Hardware Verification Language. As you might already know, hardware (computer chips) is designed using a Hardware Description Language (VHDL, Verilog) which is then synthesized into gates like NOR, NAND and sequential elements like Flip-Flops. So before you do synthesis, which is a tedious process, you would want to make sure that the functionality aspect of your HDL-constructed design looks good.

With System Verilog, you are able to create complex testbench structures and perform simulations to verify the design. You are essentially making sure that the code you have written with verilog functions well and implements features that you intend to. To know more about System Verilog follow link : Introduction to System Verilog

Save time on re-compilation of the TB with an exte...
about the UVM queue class ?


No comments made yet. Be the first to submit a comment
Already Registered? Login Here
Monday, 25 June 2018

We use cookies to personalize content and ads, to provide social media features and to analyze our traffic. You consent to our cookies if you continue to use our website. To find out more about the cookies we use and how to delete them, see our privacy policy.

  I accept cookies from this site.
EU Cookie Directive plugin by www.channeldigital.co.uk