Tests can be run in a UVM environment by either specifying the testname as an argument to
run_test() or as a command-line argument using
+UVM_TESTNAME="[test_name]". This can be considered an entry point to how UVM starts each component, configures and runs a simulation. There are a set of UVM core services within the structure, capable of providing instances to the factory and the root object. We'll see how the general flow looks like in the short explanation that follows.
module tb_top; // Import required packages import uvm_pkg::*; // Instantiate DUT and interfaces dut dut0 (...); dut_if _if0 (...); // Call run_test(); initial begin run_test ("base_test"); end endmodule
run_test( ) within tb_top as shown above, is a global task which is responsible for getting a reference to the
uvm_root class instance from UVM core services. There is another run_test( ) method within
uvm_root to initialize factory settings, report servers, and do basic level checks to ensure that you have either provided a proper testname or that atleast one component has been declared in the environment upon which UVM can work.
The main component that controls simulation in a UVM environment is the
uvm_phase class instance. This will start running phases one by one using
m_run_phases() method. The report server records all the INFO, WARNING and ERROR messages generated by various testbench components throughout the simulation. Once all the phases are over, a summary will be printed out, and simulation will exit via