Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !
Want to say something, anything, just to be there on the front page.

Practical example of polymorphism in UVM

Practical example of polymorphism in UVM

UVM factory mechanism makes the testbench more flexible and re-usable by allowing components to be overriden via the type_id::create() method. The idea is that at run-time, an object of the overridden data-type will be returned instead of the original. However, it might give a compilation error when a member of the new sub-class component is being accessed in the new environment unless properly casted. This post will describe the scenario and how to overcome the error by casting.

Continue reading
Tags:
uvm
  2263 Hits
  0 Comments

Save time on re-compilation of the TB with an external configuration file

Save time on re-compilation of the TB with an external configuration file

The testbench I was working on took quite some time to compile, elaborate and output an executable file. The design is an interconnect that has mappings from different masters to various slaves and has service registers within it accessible by specific masters. There were a block of registers for each master that would control how the transactions from the master would behave, and this required writing a lot of sequences to configure and simulate different configurations for each register. I wanted a better way to run and test a particular register set configuration without re-compiling the entire testbench and design.

Continue reading
  907 Hits
  0 Comments

Closed Loop verification

Closed Loop verification

Recently, I had the opportunity to verify a compression algorithm block that went into one of the IP's that was being developed in-house. There were two blocks involved in which the first one writes data into a memory buffer using a compression algorithm, and the second module reads the data to decompress them on the fly, perform some operations and send the processed data to some other block in the SoC subsystem. The purpose is to verify the decompression part of the whole data flow, and the best way to do that is described in the next section.

Continue reading
  1652 Hits
  0 Comments

How to play in EDA Playground

EDA Playground is a nice online website to run simulations. So, how do you "play" in that ground ? Let me give you a quick tutorial on how to use that site, and you can simply copy-paste all the code examples within ChipVerify into the playground and run simulations. Hmm, that sounds easy doesn't it ?

Continue reading
  2022 Hits
  0 Comments

We use cookies to personalize content and ads, to provide social media features and to analyze our traffic. You consent to our cookies if you continue to use our website. To find out more about the cookies we use and how to delete them, see our privacy policy.

  I accept cookies from this site.
Agree
EU Cookie Directive plugin by www.channeldigital.co.uk