Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !
Disclaimer: What I express on this site is my own personal view and is not related to the company I work for in any way.

Using a custom sample function for functional coverage

custom-sample

The first way to sample covergroups is to specify an event like clock edge or an event handle that can be triggered from elsewhere in the testbench. The second way to sample covergroups is to explicitly call sample() at places where we want the variables to be sampled. The first method is usually preferred for repetitive sampling at regular event triggers. For example, we can sample the variables on every positive edge of the clock or whenever an event called "interrupt" happens. The best way to sample values at a set of specific places in the testbench is to call sample() method as required.

Continue reading
  6535 Hits
  0 Comments

HDL routines for error injection

err-inj

There are times when a signal within the design has to be probed or monitored for certain tasks in the testbench. Typically these are accessed via hierarchical references and tend to break when the same code is ported to different projects because of changes in design hierarchy. UVM has a set of DPI implementation tasks for backdoor accesses that has a similar effect and achieves much better code reusability.

Continue reading
  375 Hits
  0 Comments

Stressing the interconnect for performance bugs

mmms

In an earlier post, I had given a small introduction on why performance verification is necessary for today's system on chips, along with a few key metrics that can be measured. Since any system will have multiple masters and multiple slaves, it is quite important to exercise these elements in various combinations such that the fabric is stressed and its internal arbiters and buffers are exhausted.

Continue reading
  1042 Hits
  0 Comments

Importance of interconnect performance verification

interconnect

An interconnect is the backbone of any system as many processor cores, DMA, graphic engines, memory and other I/O devices connect to it. Performance requirements have undergone a steep climb in today's sophisticated world where electronic chips can be found everywhere including consumer appliances, healthcare, industrial controls, and automobiles. Whatever the field may be, the consumer always expect top notch performance without any visible lag or mediocre user experience. Hence, in recent years another field of verification has sprung up in additional to functional - performance.

Continue reading
  1062 Hits
  0 Comments

Working with register object configurations

rm

What I like about the register layer in UVM is that it provides a very convenient interface to program registers in a design with minimal trouble. I said minimal because I feel that it is still under the process of evolvement to provide the user with a complete set of API, and hence might require a little work-around here and there - or well, it could be that I haven't found the right solution yet. So, I am going to describe an out of the way approach I used recently to randomize registers to my whims and selectively write certain registers.

Continue reading
Recent comment in this post
Stephen van den Elshout
Nice site!
Thursday, 03 August 2017 14:09
  1059 Hits
  1 Comment

`uvm_create 'd name of an object

`uvm_create 'd name of an object

UVM sequence macros are a great way of reducing code and hiding away some details. `uvm_do macros enable a sequence item to be created, randomized and executed on a sequencer all from a single line of code. `uvm_create is another macro which simply creates an object of a sequence item so that it can be handled later on. Let's see what the name of an object created by `uvm_create would look like. Unlike a typical type_id::create() method where you get to specify a required name, `uvm_create does not have any, not that it matters, but just for trivia.

Continue reading
  1372 Hits
  0 Comments

that you have to reset your register model ?

that you have to reset your register model ?

In the UVM world there exists a function to reset a register block within a model. This is a step that many beginners often overlook because the need to invoke this might not be very clear until errors crop up. The register model primarily holds three different kinds of values each for a different purpose. Let's see how the reset() method affects each of them.

Continue reading
  2492 Hits
  0 Comments

Remove redundant register sequences with this neat trick

Remove redundant register sequences with this neat trick

I was sipping green tea sitting in front of my desk trying to figure a way to avoid having to write redundant sequences and register model method calls. That's when I got this idea to check upon existing methods in the UVM register layer. Well, good that I did ! I saved quite a lot of time writing sequences by the effective use of uvm_reg_block and uvm_reg methods.

Continue reading
Recent comment in this post
Nayan Naware
Can you please include the basics of RAL and its implementation. So that one who is starting with RAL can understand it more clear... Read More
Monday, 24 July 2017 01:14
  1805 Hits
  1 Comment

how to create a singleton object

how to create a singleton object

Creating a global singleton object that can be referenced from elsewhere in the testbench is sometimes a good thing. This is very similar to the way static variables in a class work - only one variable is created and made accessible for all class objects. In this case, a single class object is created that can be accessed from other testbench components. As an example, you could have such a class object to contain all the design or testbench specification features like number of masters and slaves, or clock frequency requirements for each interface, etc. Let's see how to effectively create a singleton object.

Continue reading
  1956 Hits
  0 Comments

about the UVM queue class ?

about the UVM queue class ?

Yes. UVM has a class-based dynamic queue that can be allocated on demand, passed and stored by reference. Eventhough uvm_queue is a parameterized class extended from uvm_object, it is not registered with the factory and hence invocation of new() function is the correct way to create a queue object.

Continue reading
  3172 Hits
  0 Comments

how to pass a command line argument to UVM testbench ?

how to pass a command line argument to UVM testbench ?

At times we might need to accept values from the command line to make our testbench and testcases more flexible. UVM provides this support via the uvm_cmdline_processor singleton class. Generation of the data structures which hold the command line arguments happen during construction of the class object. A global variable called uvm_cmdline_proc is created at initialization time which can be used to access command line options. Let's see more on how this feature can be used.

Continue reading
  3306 Hits
  0 Comments

$deposit - Put a value onto any net/register

$deposit - Put a value onto any net/register

A few months ago, I was involved in writing a couple of tests that had to be run using RTL netlists with scan chains in them. Since this involved a lot of gate level signals, it was already cumbersome to debug. The idea was to enter the scan mode and shift out values in the chain and then be able to observe the value of a particular flop, after so many cycles at the output pad. So, there was a need to check if we got the right value at the pin after scan entry.

Continue reading
  3641 Hits
  0 Comments

how to disable file name and line numbers in reports

how to disable file name and line numbers in reports

UVM has this nice feature of being able to print the line number and file name from where a reporting task is called. This is very helpful during the early days of testbench debug, but it can soon clutter the log reports. Just imagine having the file name occupy most of the screen space, true in most projects because of the long path to a file, only to make it difficult for you to find the actual report message. Good News ! There's a way to disable this.

Continue reading
Recent Comments
Aravind Prakash
+define option is required to be given during compilation. As you might already know, the tool essentially needs to do three thing... Read More
Tuesday, 20 February 2018 17:24
  2341 Hits
  2 Comments

what happens when you register a component with factory ?

what happens when you register a component with factory ?

One of the main features of UVM is the factory mechanism, and we already know how to use `uvm_component_utils () and `uvm_object_utils () within user-defined component and object classes. It's a way of registering our new component with the factory so that we can request the factory to return an object of some other type later on via type_id::create () method. Let's see what happens behind the scene when the code is elaborated and compiled for the example that follows.

Continue reading
Recent Comments
Ratiranjan Senapati
Thanks a lot Aravind. Thanks for all your easy explanations. Helped a lot. Please keep it up ... Read More
Saturday, 08 October 2016 00:56
Rupam Kumari
Thanks for all your easy explanations. It helped me alot.
Monday, 11 September 2017 23:24
  2323 Hits
  2 Comments

how to turn an agent from active to passive ?

how to turn an agent from active to passive ?

An agent is a hierarchical block which puts together other verification components that are dealing with a specific DUT interface. It usually contains a sequencer to generate data transactions, a driver to drive these transactions to the DUT, and a monitor that sits on the interface and tries to capture the pin wiggling that happens on the DUT interface. So, in a typical UVM environment there'll be multiple agents connected to various interfaces of the DUT. Sometimes, we do not want to drive anything to the DUT, but simply monitor the data produced by DUT. It would be nice to have a feature to turn the sequencer and driver of an agent ON and OFF when required.

Continue reading
  3672 Hits
  0 Comments

how to set a timeout value for simulations ?

how to set a timeout value for simulations ?

There are ocassions when some components in the testbench keep running forever and cause the simulation to hang. Another case is when performing SoC level C tests, where you could have written a while (1) code expecting an interrupt to cause the loop to break but, instead not get the interrupt at all. Not a good place to be in, especially if you tried running it in your local machine instead of an LSF farm. Let's look at what UVM has to offer to get around this.

Continue reading
  5840 Hits
  0 Comments

how run_test( ) starts the simulation ?

how run_test( ) starts the simulation ?

Tests can be run in a UVM environment by either specifying the testname as an argument to run_test() or as a command-line argument using +UVM_TESTNAME="[test_name]". This can be considered an entry point to how UVM starts each component, configures and runs a simulation. There are a set of UVM core services within the structure, capable of providing instances to the factory and the root object. We'll see how the general flow looks like in the short explanation that follows.

Continue reading
Recent Comments
Chaitanya Kshirsagar
run_test() will start executing phsese, but how function new() in components and object get executed?
Thursday, 24 November 2016 22:30
Aravind Prakash
function new() is a class constructor and will always be executed when an object of that class is created. In UVM, objects are nor... Read More
Friday, 25 November 2016 06:10
  4067 Hits
  2 Comments

SimVision Video Series

Continue reading
Recent comment in this post
Aravind Prakash
Really useful. Thanks for sharing !
Thursday, 24 September 2015 13:54
  1390 Hits
  1 Comment

Code Unreachability Analysis

Code Unreachability Analysis

Coverage metrics are widely used in SV/UVM verification to improve quality of the test suite and estimate the effort required to finish the verification task. They indicate how much of the design code has been exercised by existing set of tests, and provide an idea of how to write future tests that can target certain coverage holes. You can perform a code and functional coverage analysis after every regression to identify how many tests should be developed in order to target specific features of the design. Many times you'll find that in spite of trying every combination of input stimuli, there are certain pieces of code that simply does not get hit or exercised in simulation. You might have stumbled onto something called as unreachable code or dead code. As the name implies, it is part of the source code of a program or RTL that can never be executed because there is no control path to the code. Dead code can also be a piece of code that may be executed but does produce any effect on the output.

Continue reading
Recent Comments
Aravind Prakash
You may call it dead code, but in the proper sense it's not. Part of the code is unreachable only when you tie the control signal ... Read More
Wednesday, 09 March 2016 06:33
Jose Luis Cueva
Hi Aravind This works to find Unreachable FSM states ? Thanks
Tuesday, 16 May 2017 10:10
Aravind Prakash
Hello Jose, I would assume that vendor tools should be able to find unreachable states, although I haven't tried it myself. The li... Read More
Tuesday, 16 May 2017 17:09
  2101 Hits
  5 Comments

Closed Loop verification

Closed Loop verification

Recently, I had the opportunity to verify a compression algorithm block that went into one of the IP's that was being developed in-house. There were two blocks involved in which the first one writes data into a memory buffer using a compression algorithm, and the second module reads the data to decompress them on the fly, perform some operations and send the processed data to some other block in the SoC subsystem. The purpose is to verify the decompression part of the whole data flow, and the best way to do that is described in the next section.

Continue reading
  1668 Hits
  0 Comments

We use cookies to personalize content and ads, to provide social media features and to analyze our traffic. You consent to our cookies if you continue to use our website. To find out more about the cookies we use and how to delete them, see our privacy policy.

  I accept cookies from this site.
Agree
EU Cookie Directive plugin by www.channeldigital.co.uk