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Overriding covergroups

covergroup-inheritance

In a previous post, we saw that covergroups are also inherited by child classes and the result of sample() on coverage of both base and child classes. Although we can keep building new covergroups in each derived child class, it would be worth to explore if the same covergroup can be overridden with a new set of coverpoints and bins in the child class.

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Inheritance of covergroups

covergroup-inheritance

Object oriented programming has a feature called inheritance that allows child classes to inherit members from its parent class without having to redeclare them in the child class. It's a great way to reuse existing code, and to make changes to testbenches without touching the base class structure. A covergroup is a System Verilog keyword that allows the user to declare and define the variables to be sampled for functional coverage. In this post, I'll just share what simulation results tell us about how inherited covergroups behave and how their coverage numbers are affected.

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Using a central database to store parameters in SV

central-db

An interconnect is the backbone of an SoC as many cores, IPs and memory blocks are connected to it and hence is usually an important part of the verification plan. Each master and slave would probably be running on different clocks, have different data bus-widths and hence different requirements. From a testbench perspective, it would be interesting to think about how to organize all these design parameters so that any change in the design results in a lower effort to reflect that change in the testbench. This post will describe one way to do that in a System-Verilog based testbench.

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Practical example of polymorphism in UVM

Practical example of polymorphism in UVM

UVM factory mechanism makes the testbench more flexible and re-usable by allowing components to be overriden via the type_id::create() method. The idea is that at run-time, an object of the overridden data-type will be returned instead of the original. However, it might give a compilation error when a member of the new sub-class component is being accessed in the new environment unless properly casted. This post will describe the scenario and how to overcome the error by casting.

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uvm
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Uniquely constrain variables

Uniquely constrain variables

One of the most commonly asked questions in System Verilog for interviews is how to uniquely constrain any given array, or any two variables. There are a couple of workarounds for this, but we didn't have a clean shortcut to achieve this very useful functionality until the 2012 IEEE revision.

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how to randomize selected variables only

how to randomize selected variables only

Constrained randomization is a powerful feature of System Verilog that are generally applied to members of class objects which can be later extended, inherited and overridden. Sometimes we do not need the full blown feature set provided by classes to perform simple variable randomizations and would probably hesitate to create a class structure just to hold such variables. A simpler mechanism to randomize data that do not belong to a class is provided by the scope randomization function std::randomize().

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about the let construct in System Verilog ?

about the let construct in System Verilog ?

Many a time I have written functions that end up having only a single line of code in it and wished for a better alternative. System Verilog (1800-2009) has a construct called let that defines a template expression that can be used for customization and text replacement.

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Save time on re-compilation of the TB with an external configuration file

Save time on re-compilation of the TB with an external configuration file

The testbench I was working on took quite some time to compile, elaborate and output an executable file. The design is an interconnect that has mappings from different masters to various slaves and has service registers within it accessible by specific masters. There were a block of registers for each master that would control how the transactions from the master would behave, and this required writing a lot of sequences to configure and simulate different configurations for each register. I wanted a better way to run and test a particular register set configuration without re-compiling the entire testbench and design.

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What is SystemVerilog ?

What is SystemVerilog ?

It's a Hardware Verification Language. As you might already know, hardware (computer chips) is designed using a Hardware Description Language (VHDL, Verilog) which is then synthesized into gates like NOR, NAND and sequential elements like Flip-Flops. So before you do synthesis, which is a tedious process, you would want to make sure that the functionality aspect of your HDL-constructed design looks good.

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When an X on clock almost went unnoticed

When an X on clock almost went unnoticed

One of the first few items in the checklist for a failing testcase is the clock to the module. Usually an external crystal oscillator would be fed into a PLL block within the SoC to obtain and supply derivative clocks to all other parts of the system. So if a peripheral module does not respond when its control registers are being read it would be helpful to check if the clocks to the module are running and are of the correct frequency along with top level connections.

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Recent Comments
Suguresh Kumar Arali
Hey Admn, there is slight typo mistake in code "assign gatedClk = gateEn && clk;" please make necessary changes. and one more do... Read More
Monday, 07 August 2017 00:39
Admin
Thanks for catching that, HTML format interpreted the ampersand symbol in a different way. I just happened to see X on the clock i... Read More
Monday, 07 August 2017 06:58
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what is the m_sequencer ?

what is the m_sequencer ?

There are primarily two ways to start a sequence : use a `uvm_do macro, or use the start() method. If you have read How to execute sequences via `uvm_do macros ?, you might already know that `uvm_do macros eventually call the start() method, and the macros act as a wrapper to execute both data items and sequences on the default sequencer "m_sequencer".

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Recent Comments
Shrikant saxena
Hello sir, I have read your blog on sequencer and it is very helpful for me. but i have an doubt that can be not use TLM get/pu... Read More
Tuesday, 16 August 2016 05:44
Admin
What makes uvm_driver different from a uvm_component is that it contains a port called seq_item_port of type uvm_seq_item_pull_por... Read More
Thursday, 18 August 2016 14:49
Rahul Marotkar
we can use TLM get/put methods instead of seq_item_port.get_next_item/seq_item_port.item_done() methods. for example, we are havin... Read More
Wednesday, 22 March 2017 04:12
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System Use Cases

As you might already know, modern SoC chips integrate many IPs and peripheral blocks which might be grouped together to form certain sub-systems. For example, a camera subsystem might capture signals from a device placed outside via MIPI CSI2 interface, process it using a graphic engine, and an internal DMA could send the processed data to some location in memory. Since a sub-system contains multiple IPs/peripherals, we will have to write vectors to test the basic functionalities of each block. Taking the example above, we want to know if all the MIPI lanes have been exercised, or if the graphic engine has had some kind of transaction to all the modules connected to it.

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Verification

Verification
What is verification ?

Functional verification is the process of verifying that the logic design conforms to specification. For example, if the design is a simple 4-bit counter, functionally speaking, the counter should count from 0000 to 1111 and roll back to 0000. Verification is the task of verifying that the counter "does what it is supposed to do" - count from 0000 to 1111. If the design has some fault, and the count stops at 1100, then there's a bug in the design, which needs to be corrected. As you can see, this will make or break the design. In modern computer chips, it is very important to perform functional verification before the chip is sent for production. You wouldn't want to buy a product which contains a chip that doesn't work right ?

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C to Object Code

C to Object Code

ARM based SoC's are very common these days in the mobile/tablet market space and other consumer electronics. In a SoC verification environment, C tests are written to exercise data transactions across various IPs in the system. C tests are converted to object code following the procedure described on this page. The object code is then loaded into memory models for the processor to execute. So, let's try to learn how a C program stored in hard disk is transformed into a program executed on a processor. There are basically four logical steps/phases that you need to be aware of.

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What is SoC verification ?

These days, SoCs are assembled by a lot of in-house and third party IP's. Integration of many processor cores and IP's is a challenging task. It is even more challenging to verify the various scenarios that comes with such complex designs. It has become essential to perform a hardware-software co-verification to cover functionalities presented by both hardware and software structures.

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Recent comment in this post
Mangali BalaRaju
can u please share more information regarding Soc?? thank you.
Monday, 31 July 2017 22:15
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How to play in EDA Playground

EDA Playground is a nice online website to run simulations. So, how do you "play" in that ground ? Let me give you a quick tutorial on how to use that site, and you can simply copy-paste all the code examples within ChipVerify into the playground and run simulations. Hmm, that sounds easy doesn't it ?

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